JPS5464432A - Memory drive circuit - Google Patents
Memory drive circuitInfo
- Publication number
- JPS5464432A JPS5464432A JP13134277A JP13134277A JPS5464432A JP S5464432 A JPS5464432 A JP S5464432A JP 13134277 A JP13134277 A JP 13134277A JP 13134277 A JP13134277 A JP 13134277A JP S5464432 A JPS5464432 A JP S5464432A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- write
- clock
- circuit
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Television Signal Processing For Recording (AREA)
- Television Systems (AREA)
- Static Random-Access Memory (AREA)
- Synchronizing For Television (AREA)
Abstract
PURPOSE:To avoid malfunction, by providing overlapped part timingly between the phase comparison reference signals of a plurality, discriminating the phase of write- in clock with this signal, and driving the address and write-in register with the selection of clocks different in the phases. CONSTITUTION:In the memory driving circuit performing the memory readout and write-in with different synchronism, RAM 4 connected to the multiplexer 11 providing timingly duplicated part between the phase reference signals of a plurality is provided. Further, the readout clock generating circuit 13 discriminating the phase of the write-in clock with the output signal of RAM 4 and the phase discrimination circuit 15 selecting one clock out of the clocks of a plurality different in phase using the phase discrimination signal of the circuit 13, are provided, and the address register 10 and the write-in register 3 are driven with the clock selected with the circuit 15.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13134277A JPS5464432A (en) | 1977-10-31 | 1977-10-31 | Memory drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13134277A JPS5464432A (en) | 1977-10-31 | 1977-10-31 | Memory drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5464432A true JPS5464432A (en) | 1979-05-24 |
| JPS6143914B2 JPS6143914B2 (en) | 1986-09-30 |
Family
ID=15055690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13134277A Granted JPS5464432A (en) | 1977-10-31 | 1977-10-31 | Memory drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5464432A (en) |
-
1977
- 1977-10-31 JP JP13134277A patent/JPS5464432A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6143914B2 (en) | 1986-09-30 |
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