JPS5463612A - Vertical synchronous circuit of television image receiver - Google Patents

Vertical synchronous circuit of television image receiver

Info

Publication number
JPS5463612A
JPS5463612A JP12975077A JP12975077A JPS5463612A JP S5463612 A JPS5463612 A JP S5463612A JP 12975077 A JP12975077 A JP 12975077A JP 12975077 A JP12975077 A JP 12975077A JP S5463612 A JPS5463612 A JP S5463612A
Authority
JP
Japan
Prior art keywords
signals
level
vertical synchronizing
pulse
video signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12975077A
Other languages
Japanese (ja)
Inventor
Tsuneo Tateshimo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12975077A priority Critical patent/JPS5463612A/en
Publication of JPS5463612A publication Critical patent/JPS5463612A/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)

Abstract

PURPOSE: To obtain a sufficiently large vertical synchronizing signal pulse to prevent the step-out dependent upon ghost signals by detecting signals, which are subjected to synchronizaton separation, and extracting pulses which compensate lowering components of a level.
CONSTITUTION: Synchronizing signals are separated from composite video signals including horizontal and vertical synchronizing signals and video signals in 13, and separated synchronizing signal pulses are amplified in 14, and a part of the amplified output is supplied to peak detector circuit 32. Then, in case that the level of vertical synchronizing signals in composite video signals is lowered, a pulse which is synchronized with the level-lowered signal is obtained to extract a pulse, which compensates lowering components of the level, from inversional amplifier circuit 33, so that a sufficiently large vertical synchronizing signal pulse can be obtained.
COPYRIGHT: (C)1979,JPO&Japio
JP12975077A 1977-10-31 1977-10-31 Vertical synchronous circuit of television image receiver Pending JPS5463612A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12975077A JPS5463612A (en) 1977-10-31 1977-10-31 Vertical synchronous circuit of television image receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12975077A JPS5463612A (en) 1977-10-31 1977-10-31 Vertical synchronous circuit of television image receiver

Publications (1)

Publication Number Publication Date
JPS5463612A true JPS5463612A (en) 1979-05-22

Family

ID=15017266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12975077A Pending JPS5463612A (en) 1977-10-31 1977-10-31 Vertical synchronous circuit of television image receiver

Country Status (1)

Country Link
JP (1) JPS5463612A (en)

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