JPS5461810A - Information control system - Google Patents

Information control system

Info

Publication number
JPS5461810A
JPS5461810A JP12842177A JP12842177A JPS5461810A JP S5461810 A JPS5461810 A JP S5461810A JP 12842177 A JP12842177 A JP 12842177A JP 12842177 A JP12842177 A JP 12842177A JP S5461810 A JPS5461810 A JP S5461810A
Authority
JP
Japan
Prior art keywords
signal
information
timing signal
lines
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12842177A
Other languages
Japanese (ja)
Inventor
Saburo Nishinomiya
Ryushi Hiroya
Wataru Hyodo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12842177A priority Critical patent/JPS5461810A/en
Publication of JPS5461810A publication Critical patent/JPS5461810A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To miniaturize a controlled unit, and to simplify a circuit by holding a control timing signal by a common controller. CONSTITUTION:Channel controller SPC receiving 1st synchronizing signal ST from common controller CC and a signal through an information signal, gate G2 sets contents of information lines 8 to 15 to register R0 as device assignment information of the relay or switch. After the reception of 2nd signal ST from CC and a signal through information line O, gata G0 allows gate GRL to open and driver circuit DV is controlled by timing signal strings of lines 8 to 15. Here, the timing signal string is held in the buffer register inside CC.
JP12842177A 1977-10-26 1977-10-26 Information control system Pending JPS5461810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12842177A JPS5461810A (en) 1977-10-26 1977-10-26 Information control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12842177A JPS5461810A (en) 1977-10-26 1977-10-26 Information control system

Publications (1)

Publication Number Publication Date
JPS5461810A true JPS5461810A (en) 1979-05-18

Family

ID=14984337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12842177A Pending JPS5461810A (en) 1977-10-26 1977-10-26 Information control system

Country Status (1)

Country Link
JP (1) JPS5461810A (en)

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