JPS5459054A - Function generator - Google Patents
Function generatorInfo
- Publication number
- JPS5459054A JPS5459054A JP12631377A JP12631377A JPS5459054A JP S5459054 A JPS5459054 A JP S5459054A JP 12631377 A JP12631377 A JP 12631377A JP 12631377 A JP12631377 A JP 12631377A JP S5459054 A JPS5459054 A JP S5459054A
- Authority
- JP
- Japan
- Prior art keywords
- output
- constant
- multiplier
- adder
- distortion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/035—Reduction of table size
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Analogue/Digital Conversion (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To minimize the size of the hardware as well as to avoid the distortion of the output waveform by constituting the circuit of the time function generator used to the communication equipment and the like without including the multiplier. CONSTITUTION:Adder 12 functions to add the constant given from constant memory 11 to the 1-clock preceding output of shift registr 13. Decoder 14 decodes the output of register 13, and detects to which level among a0-a5, for instance, the output waveform has arrived to alter the addresses read out from memory 11 according to each level and then to vary the constant to be applied to adder 12. The digital word is produced at output terminal 15 and then converted to another waveform through D-A converter. The action timing is regulatd by a fixed clock for each of above mentioned component elements 11-14. Thus, no multiplier is used for the circuit, so the size of the hardware can be minimized. Furthermore, the distortion of the output waveform caused by the accumulation of the noise mixing in when gathering the multiplication results can be prevented.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12631377A JPS5459054A (en) | 1977-10-19 | 1977-10-19 | Function generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12631377A JPS5459054A (en) | 1977-10-19 | 1977-10-19 | Function generator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5459054A true JPS5459054A (en) | 1979-05-12 |
Family
ID=14932084
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12631377A Pending JPS5459054A (en) | 1977-10-19 | 1977-10-19 | Function generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5459054A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5916051A (en) * | 1982-07-19 | 1984-01-27 | Hitachi Ltd | Address arithmetic circuit |
-
1977
- 1977-10-19 JP JP12631377A patent/JPS5459054A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5916051A (en) * | 1982-07-19 | 1984-01-27 | Hitachi Ltd | Address arithmetic circuit |
JPH0215089B2 (en) * | 1982-07-19 | 1990-04-11 | Hitachi Ltd |
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