JPS5459005A - Data communication method - Google Patents

Data communication method

Info

Publication number
JPS5459005A
JPS5459005A JP12541577A JP12541577A JPS5459005A JP S5459005 A JPS5459005 A JP S5459005A JP 12541577 A JP12541577 A JP 12541577A JP 12541577 A JP12541577 A JP 12541577A JP S5459005 A JPS5459005 A JP S5459005A
Authority
JP
Japan
Prior art keywords
cpu5
circuit
station
reception
fully double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12541577A
Other languages
Japanese (ja)
Inventor
Makoto Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP12541577A priority Critical patent/JPS5459005A/en
Publication of JPS5459005A publication Critical patent/JPS5459005A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Abstract

PURPOSE:To enhance both the CPU process efficiency and the circuit using efficiency by using properly both the semidouble and fully double systems via the control of CPU. CONSTITUTION:The semidouble communication circuit is formed with CPU5 of station A and CPU5' of station B via exchange 1 and circuit C1, and then shifted to the fully double communication by the request of station A. In this case, CPU5 is connected to CPU5' via circuit C2, the control data is sent to CPU5' via circuit C1 turn circuit C1 to exclusive use for reception respectively with the indication of CPU5, and MODEM 4a and 4b are fixed to the transmission and reception made each. At station B, the control data is detected through CPU5' MODEM 4a' and 4b' are fixed to the reception and transmission modes respectively, and the confirmation data for shift end is sent to CPU5 for a fixed time. In such way, the fully double communication becomes possible.
JP12541577A 1977-10-19 1977-10-19 Data communication method Pending JPS5459005A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12541577A JPS5459005A (en) 1977-10-19 1977-10-19 Data communication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12541577A JPS5459005A (en) 1977-10-19 1977-10-19 Data communication method

Publications (1)

Publication Number Publication Date
JPS5459005A true JPS5459005A (en) 1979-05-12

Family

ID=14909530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12541577A Pending JPS5459005A (en) 1977-10-19 1977-10-19 Data communication method

Country Status (1)

Country Link
JP (1) JPS5459005A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03208431A (en) * 1989-10-11 1991-09-11 Digital Equip Corp <Dec> All double communication establishment method and device
JP2010034731A (en) * 2008-07-28 2010-02-12 Nec Infrontia Corp Notification system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03208431A (en) * 1989-10-11 1991-09-11 Digital Equip Corp <Dec> All double communication establishment method and device
JP2010034731A (en) * 2008-07-28 2010-02-12 Nec Infrontia Corp Notification system

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