JPS5457811A - Analog switching system on digital link system - Google Patents

Analog switching system on digital link system

Info

Publication number
JPS5457811A
JPS5457811A JP12418477A JP12418477A JPS5457811A JP S5457811 A JPS5457811 A JP S5457811A JP 12418477 A JP12418477 A JP 12418477A JP 12418477 A JP12418477 A JP 12418477A JP S5457811 A JPS5457811 A JP S5457811A
Authority
JP
Japan
Prior art keywords
subscriber
memory
circuit
assignment
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12418477A
Other languages
Japanese (ja)
Inventor
Saburo Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12418477A priority Critical patent/JPS5457811A/en
Publication of JPS5457811A publication Critical patent/JPS5457811A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To miniaturize a switchboard by the use of a digital link. CONSTITUTION:This system is equipped with D/A converter 1, interface circuits 2, 3 and 5, A/D converter 4, terminal-assignment-information generating circuit 6, RT-relay-state detection circuit 7, L-relay-state detection circuit 8, arithmetic processing circuit 9, buffer register memory 10, terminal assignment circuit 11, answer detection circuit 12, calling detection circuit 13, dial receiver circuit 14, No.-''0'' called-subscriber assignment information memory 15, No.-''0'' subscriber's-transmission-signal digital memory 16, memory write decoder 17, sound-reduction-data generating circuit 18, memory read decoder 19, No.-''0'' called-subscriber assignment infromation memory 20, and No.-''n'' subscriber's transmission-signal digital memory 21. An analog signal equivlent to a subscriber is mixed and sampled and its subtraction is done by the digital information of the previously mixed analog signal. Subscriber's mixed transmission signal is stored temporarily as digital information, the result through the mixing method of a party subscriber is mixed, and the transmission signal of the party subscriber is obtained through the subtraction mentioned above and stored temporarily, thereby exchanging the pieces of temporarily-stored information each other.
JP12418477A 1977-10-15 1977-10-15 Analog switching system on digital link system Pending JPS5457811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12418477A JPS5457811A (en) 1977-10-15 1977-10-15 Analog switching system on digital link system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12418477A JPS5457811A (en) 1977-10-15 1977-10-15 Analog switching system on digital link system

Publications (1)

Publication Number Publication Date
JPS5457811A true JPS5457811A (en) 1979-05-10

Family

ID=14879049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12418477A Pending JPS5457811A (en) 1977-10-15 1977-10-15 Analog switching system on digital link system

Country Status (1)

Country Link
JP (1) JPS5457811A (en)

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