JPS5456746A - Writing circuit for analog memory - Google Patents

Writing circuit for analog memory

Info

Publication number
JPS5456746A
JPS5456746A JP13851877A JP13851877A JPS5456746A JP S5456746 A JPS5456746 A JP S5456746A JP 13851877 A JP13851877 A JP 13851877A JP 13851877 A JP13851877 A JP 13851877A JP S5456746 A JPS5456746 A JP S5456746A
Authority
JP
Japan
Prior art keywords
memory
writing
reading
coincidence
operated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13851877A
Other languages
Japanese (ja)
Other versions
JPS5727559B2 (en
Inventor
Yoshinosuke Nagata
Kazuyoshi Tsukamoto
Makoto Yamada
Hiroshi Kutsuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP13851877A priority Critical patent/JPS5456746A/en
Publication of JPS5456746A publication Critical patent/JPS5456746A/en
Publication of JPS5727559B2 publication Critical patent/JPS5727559B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE: To secure accurate writing of the optional analog quantity by applying the writing pulse featuring the envelope curve of the saw-tooth wave to the memory and stopping application of new writing pulse when the reading output of the memory is in agreement with the analog quantity to be written.
CONSTITUTION: In the receiving unit which presets the tuning voltage to the analog memory, preset memory switch 103, for instance, is operated to write the writing voltage into data memory 107 through control circuit 108 as in case switch 104 and 105 are operated. Then in the reading mode, the reading output given from memory 107 is reversely amplified at converter circuit 110 and then compared with the tuning voltage generated 102. And the reading and writing modes are repeated until a coincidence is secured through the comparison. When a coincidence is obtained, the stop signal is produced from comparator 111 to inhibit the new writing
COPYRIGHT: (C)1979,JPO&Japio
JP13851877A 1977-11-16 1977-11-16 Writing circuit for analog memory Granted JPS5456746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13851877A JPS5456746A (en) 1977-11-16 1977-11-16 Writing circuit for analog memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13851877A JPS5456746A (en) 1977-11-16 1977-11-16 Writing circuit for analog memory

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP12419777A Division JPS5456701A (en) 1977-10-14 1977-10-14 Preset receiving device

Publications (2)

Publication Number Publication Date
JPS5456746A true JPS5456746A (en) 1979-05-08
JPS5727559B2 JPS5727559B2 (en) 1982-06-11

Family

ID=15224009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13851877A Granted JPS5456746A (en) 1977-11-16 1977-11-16 Writing circuit for analog memory

Country Status (1)

Country Link
JP (1) JPS5456746A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028737A (en) * 1973-07-13 1975-03-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028737A (en) * 1973-07-13 1975-03-24

Also Published As

Publication number Publication date
JPS5727559B2 (en) 1982-06-11

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