JPS5449069A - Method and device for lead correction - Google Patents

Method and device for lead correction

Info

Publication number
JPS5449069A
JPS5449069A JP11631977A JP11631977A JPS5449069A JP S5449069 A JPS5449069 A JP S5449069A JP 11631977 A JP11631977 A JP 11631977A JP 11631977 A JP11631977 A JP 11631977A JP S5449069 A JPS5449069 A JP S5449069A
Authority
JP
Japan
Prior art keywords
lead
hole
correction
deformed
setting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11631977A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6136378B2 (https=
Inventor
Hiroshi Osabe
Masao Hino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11631977A priority Critical patent/JPS5449069A/ja
Publication of JPS5449069A publication Critical patent/JPS5449069A/ja
Publication of JPS6136378B2 publication Critical patent/JPS6136378B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP11631977A 1977-09-27 1977-09-27 Method and device for lead correction Granted JPS5449069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11631977A JPS5449069A (en) 1977-09-27 1977-09-27 Method and device for lead correction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11631977A JPS5449069A (en) 1977-09-27 1977-09-27 Method and device for lead correction

Publications (2)

Publication Number Publication Date
JPS5449069A true JPS5449069A (en) 1979-04-18
JPS6136378B2 JPS6136378B2 (https=) 1986-08-18

Family

ID=14684033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11631977A Granted JPS5449069A (en) 1977-09-27 1977-09-27 Method and device for lead correction

Country Status (1)

Country Link
JP (1) JPS5449069A (https=)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5755953U (https=) * 1980-09-17 1982-04-01
JPS60206143A (ja) * 1984-03-30 1985-10-17 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6386534A (ja) * 1986-09-30 1988-04-16 Toshiba Corp フイルムキヤリアおよびその製造方法
US7061082B2 (en) 1997-02-25 2006-06-13 Micron Technology, Inc. Semiconductor die with attached heat sink and transfer mold
US7220615B2 (en) 2001-06-11 2007-05-22 Micron Technology, Inc. Alternative method used to package multimedia card by transfer molding

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5755953U (https=) * 1980-09-17 1982-04-01
JPS60206143A (ja) * 1984-03-30 1985-10-17 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6386534A (ja) * 1986-09-30 1988-04-16 Toshiba Corp フイルムキヤリアおよびその製造方法
US7061082B2 (en) 1997-02-25 2006-06-13 Micron Technology, Inc. Semiconductor die with attached heat sink and transfer mold
US7220615B2 (en) 2001-06-11 2007-05-22 Micron Technology, Inc. Alternative method used to package multimedia card by transfer molding

Also Published As

Publication number Publication date
JPS6136378B2 (https=) 1986-08-18

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