JPS5448024A - Motor controller - Google Patents

Motor controller

Info

Publication number
JPS5448024A
JPS5448024A JP11322877A JP11322877A JPS5448024A JP S5448024 A JPS5448024 A JP S5448024A JP 11322877 A JP11322877 A JP 11322877A JP 11322877 A JP11322877 A JP 11322877A JP S5448024 A JPS5448024 A JP S5448024A
Authority
JP
Japan
Prior art keywords
motor
output signal
produce
speed
abnormality
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11322877A
Other languages
Japanese (ja)
Other versions
JPS5937674B2 (en
Inventor
Hiroichiro Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP52113228A priority Critical patent/JPS5937674B2/en
Publication of JPS5448024A publication Critical patent/JPS5448024A/en
Publication of JPS5937674B2 publication Critical patent/JPS5937674B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To dicide wether it is the abnormality at load side or at controller side through logic circuit, when the speed or the torque of motor varies, by deciding wether these varying polarities are same with varying polarity of motor current.
CONSTITUTION: The speed of DC motor 10 is controlled by the power supplied from thyristor controlled power source 11. When the motor speed varies abruptly due to the abnormality at load side, current in differential amplifier 19 increases to produce positive output signal while the amplifier 20 produces nigative output signal, and AND gate 22 functions to produce a signal on terminal b. When a abnormality occurs at controller side both output signals from amplifiers 19, 20 become positive, and AND gate 21 functions to produce output signal on terminal a
COPYRIGHT: (C)1979,JPO&Japio
JP52113228A 1977-09-22 1977-09-22 Failure cause determination circuit Expired JPS5937674B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52113228A JPS5937674B2 (en) 1977-09-22 1977-09-22 Failure cause determination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52113228A JPS5937674B2 (en) 1977-09-22 1977-09-22 Failure cause determination circuit

Publications (2)

Publication Number Publication Date
JPS5448024A true JPS5448024A (en) 1979-04-16
JPS5937674B2 JPS5937674B2 (en) 1984-09-11

Family

ID=14606804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52113228A Expired JPS5937674B2 (en) 1977-09-22 1977-09-22 Failure cause determination circuit

Country Status (1)

Country Link
JP (1) JPS5937674B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5947295U (en) * 1982-09-21 1984-03-29 松下電器産業株式会社 Servo amplifier protection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5947295U (en) * 1982-09-21 1984-03-29 松下電器産業株式会社 Servo amplifier protection circuit

Also Published As

Publication number Publication date
JPS5937674B2 (en) 1984-09-11

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