JPS5432447Y2 - - Google Patents

Info

Publication number
JPS5432447Y2
JPS5432447Y2 JP1975161170U JP16117075U JPS5432447Y2 JP S5432447 Y2 JPS5432447 Y2 JP S5432447Y2 JP 1975161170 U JP1975161170 U JP 1975161170U JP 16117075 U JP16117075 U JP 16117075U JP S5432447 Y2 JPS5432447 Y2 JP S5432447Y2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1975161170U
Other versions
JPS5273669U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1975161170U priority Critical patent/JPS5432447Y2/ja
Publication of JPS5273669U publication Critical patent/JPS5273669U/ja
Application granted granted Critical
Publication of JPS5432447Y2 publication Critical patent/JPS5432447Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/1627Disposition stacked type assemblies, e.g. stacked multi-cavities
JP1975161170U 1975-11-28 1975-11-28 Expired JPS5432447Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1975161170U JPS5432447Y2 (ja) 1975-11-28 1975-11-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1975161170U JPS5432447Y2 (ja) 1975-11-28 1975-11-28

Publications (2)

Publication Number Publication Date
JPS5273669U JPS5273669U (ja) 1977-06-02
JPS5432447Y2 true JPS5432447Y2 (ja) 1979-10-08

Family

ID=28640050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1975161170U Expired JPS5432447Y2 (ja) 1975-11-28 1975-11-28

Country Status (1)

Country Link
JP (1) JPS5432447Y2 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0121568Y2 (ja) * 1987-04-09 1989-06-27
US5579207A (en) * 1994-10-20 1996-11-26 Hughes Electronics Three-dimensional integrated circuit stacking

Also Published As

Publication number Publication date
JPS5273669U (ja) 1977-06-02

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