JPS5432447Y2 - - Google Patents
Info
- Publication number
- JPS5432447Y2 JPS5432447Y2 JP1975161170U JP16117075U JPS5432447Y2 JP S5432447 Y2 JPS5432447 Y2 JP S5432447Y2 JP 1975161170 U JP1975161170 U JP 1975161170U JP 16117075 U JP16117075 U JP 16117075U JP S5432447 Y2 JPS5432447 Y2 JP S5432447Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1975161170U JPS5432447Y2 (https=) | 1975-11-28 | 1975-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1975161170U JPS5432447Y2 (https=) | 1975-11-28 | 1975-11-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5273669U JPS5273669U (https=) | 1977-06-02 |
| JPS5432447Y2 true JPS5432447Y2 (https=) | 1979-10-08 |
Family
ID=28640050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1975161170U Expired JPS5432447Y2 (https=) | 1975-11-28 | 1975-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5432447Y2 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0121568Y2 (https=) * | 1987-04-09 | 1989-06-27 | ||
| US5579207A (en) * | 1994-10-20 | 1996-11-26 | Hughes Electronics | Three-dimensional integrated circuit stacking |
-
1975
- 1975-11-28 JP JP1975161170U patent/JPS5432447Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5273669U (https=) | 1977-06-02 |