JPS54182859U - - Google Patents

Info

Publication number
JPS54182859U
JPS54182859U JP8107878U JP8107878U JPS54182859U JP S54182859 U JPS54182859 U JP S54182859U JP 8107878 U JP8107878 U JP 8107878U JP 8107878 U JP8107878 U JP 8107878U JP S54182859 U JPS54182859 U JP S54182859U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8107878U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8107878U priority Critical patent/JPS54182859U/ja
Publication of JPS54182859U publication Critical patent/JPS54182859U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP8107878U 1978-06-15 1978-06-15 Pending JPS54182859U (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8107878U JPS54182859U (enExample) 1978-06-15 1978-06-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8107878U JPS54182859U (enExample) 1978-06-15 1978-06-15

Publications (1)

Publication Number Publication Date
JPS54182859U true JPS54182859U (enExample) 1979-12-25

Family

ID=29000575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8107878U Pending JPS54182859U (enExample) 1978-06-15 1978-06-15

Country Status (1)

Country Link
JP (1) JPS54182859U (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009514250A (ja) * 2005-11-01 2009-04-02 アレグロ・マイクロシステムズ・インコーポレーテッド フリップチップ・オン・リード半導体パッケージの方法および装置
US9299915B2 (en) 2012-01-16 2016-03-29 Allegro Microsystems, Llc Methods and apparatus for magnetic sensor having non-conductive die paddle
JP2017083597A (ja) * 2015-10-27 2017-05-18 三菱電機株式会社 波長多重光通信モジュール
US10991644B2 (en) 2019-08-22 2021-04-27 Allegro Microsystems, Llc Integrated circuit package having a low profile

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009514250A (ja) * 2005-11-01 2009-04-02 アレグロ・マイクロシステムズ・インコーポレーテッド フリップチップ・オン・リード半導体パッケージの方法および装置
JP2013219369A (ja) * 2005-11-01 2013-10-24 Allegro Microsystems Llc フリップチップ・オン・リード半導体パッケージの方法および装置
KR101340576B1 (ko) * 2005-11-01 2013-12-11 알레그로 마이크로시스템스, 엘엘씨 플립 칩 온 리드 반도체 패키지 방법 및 장치
US9299915B2 (en) 2012-01-16 2016-03-29 Allegro Microsystems, Llc Methods and apparatus for magnetic sensor having non-conductive die paddle
US10333055B2 (en) 2012-01-16 2019-06-25 Allegro Microsystems, Llc Methods for magnetic sensor having non-conductive die paddle
JP2017083597A (ja) * 2015-10-27 2017-05-18 三菱電機株式会社 波長多重光通信モジュール
US10991644B2 (en) 2019-08-22 2021-04-27 Allegro Microsystems, Llc Integrated circuit package having a low profile

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