JPS54161222A - Recording-reproducing display unit for output of high speed frame-by-frame television camera - Google Patents
Recording-reproducing display unit for output of high speed frame-by-frame television cameraInfo
- Publication number
- JPS54161222A JPS54161222A JP7049478A JP7049478A JPS54161222A JP S54161222 A JPS54161222 A JP S54161222A JP 7049478 A JP7049478 A JP 7049478A JP 7049478 A JP7049478 A JP 7049478A JP S54161222 A JPS54161222 A JP S54161222A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- signal
- synchronizing signal
- recording
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
PURPOSE: To display a picture, obtained by recording and reproducing the output signal of a high- speed frame-by-frame television camera available for a frame pickup more than twice as many as image trucks per second of a helical scan system VTR used only for internal synchronization on a monitor without hindrance.
CONSTITUTION: This unit consists of helical scan system VTR 14 exclusively used for internal synchronization available for recording on a fixed number of video trucks per second; TV camera 11 available for a frame pickup more than twice as many as trucks per second, synchronizing signal generator 12, composite synchronizing generating circuit 30, mixer 13 connected to the input side of VTR 14, demodulation circuit 50, and mixer circuit 15. Here, synchronizing signal generator 12 adds a synchronizing signal of a fixed frequency and a reference frame signal of a frequency equivalent to the number of trucks to the output signal of camera 11 between frame signals. Then, mixer 13 supplies a modulated frame-synchronizing signal modulated by a burst signal between frame signals supplied with no synchronizing signal; and demodulation circuit 50 detects the frame-synchronizing signal by receiving the output of VTR 14 and mixer circuit 15 adds the detected framesynchronizing signal to the regenerated signal.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7049478A JPS54161222A (en) | 1978-06-12 | 1978-06-12 | Recording-reproducing display unit for output of high speed frame-by-frame television camera |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7049478A JPS54161222A (en) | 1978-06-12 | 1978-06-12 | Recording-reproducing display unit for output of high speed frame-by-frame television camera |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54161222A true JPS54161222A (en) | 1979-12-20 |
Family
ID=13433120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7049478A Pending JPS54161222A (en) | 1978-06-12 | 1978-06-12 | Recording-reproducing display unit for output of high speed frame-by-frame television camera |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54161222A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0257074A (en) * | 1988-08-23 | 1990-02-26 | Nec Corp | Solid-state image pickup device |
-
1978
- 1978-06-12 JP JP7049478A patent/JPS54161222A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0257074A (en) * | 1988-08-23 | 1990-02-26 | Nec Corp | Solid-state image pickup device |
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