JPS54159828A - Dynamic memory unit - Google Patents

Dynamic memory unit

Info

Publication number
JPS54159828A
JPS54159828A JP6826678A JP6826678A JPS54159828A JP S54159828 A JPS54159828 A JP S54159828A JP 6826678 A JP6826678 A JP 6826678A JP 6826678 A JP6826678 A JP 6826678A JP S54159828 A JPS54159828 A JP S54159828A
Authority
JP
Japan
Prior art keywords
address information
dynamic memory
memory
memory unit
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6826678A
Other languages
Japanese (ja)
Inventor
Makoto Imamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6826678A priority Critical patent/JPS54159828A/en
Publication of JPS54159828A publication Critical patent/JPS54159828A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To eliminate malfunctions without address change by inhibiting the change of the output of a buffer register by gate pulses which perform the refresh of the memory. CONSTITUTION:Row address information RAD1 and column address information CAD1 are written in buffer register 13 when the second strobe signal ST2 is high- level, and the write is stopped when this signal is low-level. As a result, address information is not supplied to memory 11 during the refresh operation time of dynamic memory 11.
JP6826678A 1978-06-08 1978-06-08 Dynamic memory unit Pending JPS54159828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6826678A JPS54159828A (en) 1978-06-08 1978-06-08 Dynamic memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6826678A JPS54159828A (en) 1978-06-08 1978-06-08 Dynamic memory unit

Publications (1)

Publication Number Publication Date
JPS54159828A true JPS54159828A (en) 1979-12-18

Family

ID=13368766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6826678A Pending JPS54159828A (en) 1978-06-08 1978-06-08 Dynamic memory unit

Country Status (1)

Country Link
JP (1) JPS54159828A (en)

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