JPS54158968A - Time set system - Google Patents

Time set system

Info

Publication number
JPS54158968A
JPS54158968A JP6810278A JP6810278A JPS54158968A JP S54158968 A JPS54158968 A JP S54158968A JP 6810278 A JP6810278 A JP 6810278A JP 6810278 A JP6810278 A JP 6810278A JP S54158968 A JPS54158968 A JP S54158968A
Authority
JP
Japan
Prior art keywords
alarm
timer
key
time
thru
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6810278A
Other languages
Japanese (ja)
Inventor
Akira Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP6810278A priority Critical patent/JPS54158968A/en
Publication of JPS54158968A publication Critical patent/JPS54158968A/en
Pending legal-status Critical Current

Links

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  • Electric Clocks (AREA)

Abstract

PURPOSE: To enable set operation to be simply, quickly and accurately performed by so arranging the system that timer ON-OFF and alarm set may be made entirely independently by the ten keys and operation set key in the key input part.
CONSTITUTION: The frequency, oscillation frequency, etc. of the basic clock signal from a timing signal generating circuit TSG are set in a register R0 for watch. Arbitrary times such as timer ON-OFF times, alarm time, etc. are set in registers R1 thru R4 for alarm timers through key operation in a key input part 1 and at the same time the flags indicating the contents thereof are stored. The current time in the register R0 for watch and the contents of the registers R1 thru R4 for alarm timers are compared and detected in an adder circuit 27. The content of the coincided set time is judged from the flag and the alarm operation and timer ON-OFF operation corresponding to that flag are effected.
COPYRIGHT: (C)1979,JPO&Japio
JP6810278A 1978-06-06 1978-06-06 Time set system Pending JPS54158968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6810278A JPS54158968A (en) 1978-06-06 1978-06-06 Time set system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6810278A JPS54158968A (en) 1978-06-06 1978-06-06 Time set system

Publications (1)

Publication Number Publication Date
JPS54158968A true JPS54158968A (en) 1979-12-15

Family

ID=13364032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6810278A Pending JPS54158968A (en) 1978-06-06 1978-06-06 Time set system

Country Status (1)

Country Link
JP (1) JPS54158968A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5066111A (en) * 1973-10-12 1975-06-04

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5066111A (en) * 1973-10-12 1975-06-04

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