JPS54146923A - Sound multiple signal receiving circuit of tv receiver and so on - Google Patents
Sound multiple signal receiving circuit of tv receiver and so onInfo
- Publication number
- JPS54146923A JPS54146923A JP5628978A JP5628978A JPS54146923A JP S54146923 A JPS54146923 A JP S54146923A JP 5628978 A JP5628978 A JP 5628978A JP 5628978 A JP5628978 A JP 5628978A JP S54146923 A JPS54146923 A JP S54146923A
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- sub
- channel signals
- signals
- hpf
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/60—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals
- H04N5/607—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals for more than one sound signal, e.g. stereo, multilanguages
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Receiver Circuits (AREA)
Abstract
PURPOSE:To omit parts to make this circuit suitable for an IC by substituting a HPF and a shift register for the BPF for sub-channel signal separation. CONSTITUTION:FM-FM sound multiple signals are inputted to a HPF which is operated as a LPF for main channel signals and a HPF for sub-channel signals. Main channel signals are separated and are applied to L R signal selector switches SL1 and SL2. Sub-channel signals are applied to shift register SR. The shift register is driven by clocks obtained by subjecting chrominance subcarrier signals of 3.58M HZ, which are obtained in the TV receiver, to frequency division. The shift register is constituted by connecting flip flops in plural stages, and a desired delay time is obtained and pulse count detection is performed on a basis of the number of these stages. Demodulated sub-channel signals are applied to L R signal selector switches.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53056289A JPS5816835B2 (en) | 1978-05-10 | 1978-05-10 | Audio multiplex signal receiving circuit for TV receivers, etc. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53056289A JPS5816835B2 (en) | 1978-05-10 | 1978-05-10 | Audio multiplex signal receiving circuit for TV receivers, etc. |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54146923A true JPS54146923A (en) | 1979-11-16 |
JPS5816835B2 JPS5816835B2 (en) | 1983-04-02 |
Family
ID=13022930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53056289A Expired JPS5816835B2 (en) | 1978-05-10 | 1978-05-10 | Audio multiplex signal receiving circuit for TV receivers, etc. |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5816835B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS632037U (en) * | 1986-06-21 | 1988-01-08 |
-
1978
- 1978-05-10 JP JP53056289A patent/JPS5816835B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5816835B2 (en) | 1983-04-02 |
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