JPS54144138A - Pattern cut out system in character reader of the like - Google Patents

Pattern cut out system in character reader of the like

Info

Publication number
JPS54144138A
JPS54144138A JP5245178A JP5245178A JPS54144138A JP S54144138 A JPS54144138 A JP S54144138A JP 5245178 A JP5245178 A JP 5245178A JP 5245178 A JP5245178 A JP 5245178A JP S54144138 A JPS54144138 A JP S54144138A
Authority
JP
Japan
Prior art keywords
pattern
memory
signal
cut out
logical sum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5245178A
Other languages
Japanese (ja)
Inventor
Morio Yuasa
Shuji Tsuji
Nobukazu Nasuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP5245178A priority Critical patent/JPS54144138A/en
Publication of JPS54144138A publication Critical patent/JPS54144138A/en
Pending legal-status Critical Current

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  • Character Input (AREA)

Abstract

PURPOSE: To increase the conventionality of reader, by obtaining the logical sum as to each row of the character pattern data and reading out the cut out timing memory by taking the numeral in logical sum as the address.
CONSTITUTION: The video signal obtained from the image sensor 4 having the read-in elements of two dimensional arrangement, is binarized in the A/D converter 5, the binary signal for one screen's share is sequentially written in the pattern memory storing the pattern, and the pattern of the memory 8 is discriminated by receiving the specified pattern cut out timing signal. In such a unit, the pattern shift register 12 storing the video signal from the sensor 4, and the OR gate 11 inputting the logical sum between the output of the register 12 and the one video element signal binarized to the register 12, are provided, and the signal of logical sum is taken as the address and the cut out timing memory 13 is accessed. The signal displaying the address corresponding to the cut out timing in advance is put in the memory 13 to determine the readout timing of the memory 8 every time when the pattern for one video element's share is obtained.
COPYRIGHT: (C)1979,JPO&Japio
JP5245178A 1978-05-01 1978-05-01 Pattern cut out system in character reader of the like Pending JPS54144138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5245178A JPS54144138A (en) 1978-05-01 1978-05-01 Pattern cut out system in character reader of the like

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5245178A JPS54144138A (en) 1978-05-01 1978-05-01 Pattern cut out system in character reader of the like

Publications (1)

Publication Number Publication Date
JPS54144138A true JPS54144138A (en) 1979-11-10

Family

ID=12915079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5245178A Pending JPS54144138A (en) 1978-05-01 1978-05-01 Pattern cut out system in character reader of the like

Country Status (1)

Country Link
JP (1) JPS54144138A (en)

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