JPS54137937A - Time delay generating circuit of information processor - Google Patents

Time delay generating circuit of information processor

Info

Publication number
JPS54137937A
JPS54137937A JP4567278A JP4567278A JPS54137937A JP S54137937 A JPS54137937 A JP S54137937A JP 4567278 A JP4567278 A JP 4567278A JP 4567278 A JP4567278 A JP 4567278A JP S54137937 A JPS54137937 A JP S54137937A
Authority
JP
Japan
Prior art keywords
delay
time
register
content
time delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4567278A
Other languages
Japanese (ja)
Inventor
Hiroshi Horii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4567278A priority Critical patent/JPS54137937A/en
Publication of JPS54137937A publication Critical patent/JPS54137937A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable a central processor function to stop the control for any time at any position of a program.
CONSTITUTION: The operation code part is given content DELAY indicating delay, and the time count part is also given information (m) on delay time. Once this DELAY instruction is supplied, (m) is set into register 1. On the other hand, the content of register 1 is counted down by one by the output of n-division counter 3 supplied with the output of basic clock signal generator 2. Then, the content of register 1 is counted down to "0", where the contents of program counter 4 is increased to return the control to the central processor. In other words, it is possible to generate delay time equal to the time obtained by multiplying the basic clock signal by m.n.
COPYRIGHT: (C)1979,JPO&Japio
JP4567278A 1978-04-18 1978-04-18 Time delay generating circuit of information processor Pending JPS54137937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4567278A JPS54137937A (en) 1978-04-18 1978-04-18 Time delay generating circuit of information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4567278A JPS54137937A (en) 1978-04-18 1978-04-18 Time delay generating circuit of information processor

Publications (1)

Publication Number Publication Date
JPS54137937A true JPS54137937A (en) 1979-10-26

Family

ID=12725871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4567278A Pending JPS54137937A (en) 1978-04-18 1978-04-18 Time delay generating circuit of information processor

Country Status (1)

Country Link
JP (1) JPS54137937A (en)

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