JPS54133055A - Power reset circuit - Google Patents

Power reset circuit

Info

Publication number
JPS54133055A
JPS54133055A JP4018178A JP4018178A JPS54133055A JP S54133055 A JPS54133055 A JP S54133055A JP 4018178 A JP4018178 A JP 4018178A JP 4018178 A JP4018178 A JP 4018178A JP S54133055 A JPS54133055 A JP S54133055A
Authority
JP
Japan
Prior art keywords
circuit
signal
voltage
power supply
delay circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4018178A
Other languages
Japanese (ja)
Inventor
Choji Ogami
Koichi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4018178A priority Critical patent/JPS54133055A/en
Publication of JPS54133055A publication Critical patent/JPS54133055A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Landscapes

  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To ensure the reset signal, by providing the level shift circuit which shifts only a given level of the power supply voltage, delay circuit delaying the output, and gate circuit which discriminates the output of the delay circuit receiving the power supply voltage. CONSTITUTION:Before the resistor 21 and capacitor 22 constituting the delay circuit, the level shift circuit consisting of the level shift diode 31 and resistor 32 is provided. Thus, the power supply voltage Vcc from the power supply 11 is shifted by the specified level shift voltage Vs with the shift circuit, and the voltage level signal A is fed to the delay circuit. Further, the delay circuit delays this signal A and gives it to the discrimination terminal of the gate circuit 25 as the discrimination signal B, and when the voltage Vcc reaches the minimum operation voltage ML at the circuit 25, the threshold voltage TH is referred, the signal B is discriminated, and delivered as the detection signal C. Further, this signal C is fed to the reset terminal R of the external circuit 13 later.
JP4018178A 1978-04-07 1978-04-07 Power reset circuit Pending JPS54133055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4018178A JPS54133055A (en) 1978-04-07 1978-04-07 Power reset circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4018178A JPS54133055A (en) 1978-04-07 1978-04-07 Power reset circuit

Publications (1)

Publication Number Publication Date
JPS54133055A true JPS54133055A (en) 1979-10-16

Family

ID=12573602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4018178A Pending JPS54133055A (en) 1978-04-07 1978-04-07 Power reset circuit

Country Status (1)

Country Link
JP (1) JPS54133055A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49100947A (en) * 1973-01-31 1974-09-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49100947A (en) * 1973-01-31 1974-09-24

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