JPS54127645A - Full subtractor using josephson logic gate - Google Patents

Full subtractor using josephson logic gate

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Publication number
JPS54127645A
JPS54127645A JP3583878A JP3583878A JPS54127645A JP S54127645 A JPS54127645 A JP S54127645A JP 3583878 A JP3583878 A JP 3583878A JP 3583878 A JP3583878 A JP 3583878A JP S54127645 A JPS54127645 A JP S54127645A
Authority
JP
Japan
Prior art keywords
borrow
line
signals
bias current
generators
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3583878A
Other languages
Japanese (ja)
Inventor
Hideo Suzuki
Shinya Hasuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3583878A priority Critical patent/JPS54127645A/en
Publication of JPS54127645A publication Critical patent/JPS54127645A/en
Pending legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE: To simplify the constitution as well as to increase the operation speed by constituting the full sbtractor with the Josephson element.
CONSTITUTION: The parallel subtractor device consists of borrow signal generators 1-1W1-N, differential pressure signal generators 2-1W2-N, borrow signal generator bias line 3, differential pressure signal generator bias line 4 and others. Generators 2-1W2-N is formed by the circuit comprising Josephson element J1 and J2, inductance L, bias current I and external magnetic field He. After flowing the bias current to line 3, minuends A1WAN and subtrahends B1WBN are supplied to produce the borrow signals successively from the lower ranked digits. Thus, the borrow signals are generated up to the N-th digit, and then the bias current is flowed to line 4 to generate the differential signals equivalent to N digits to be obtained. Here, if the borrow signal BN of the final digit is logic "1", A - B is negative due to A<B and obtained differential signals D1WDN are complements of "2".
COPYRIGHT: (C)1979,JPO&Japio
JP3583878A 1978-03-28 1978-03-28 Full subtractor using josephson logic gate Pending JPS54127645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3583878A JPS54127645A (en) 1978-03-28 1978-03-28 Full subtractor using josephson logic gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3583878A JPS54127645A (en) 1978-03-28 1978-03-28 Full subtractor using josephson logic gate

Publications (1)

Publication Number Publication Date
JPS54127645A true JPS54127645A (en) 1979-10-03

Family

ID=12453107

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3583878A Pending JPS54127645A (en) 1978-03-28 1978-03-28 Full subtractor using josephson logic gate

Country Status (1)

Country Link
JP (1) JPS54127645A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61143842A (en) * 1984-12-14 1986-07-01 アールシーエー　トムソン　ライセンシング　コーポレイシヨン Binary subtraction stage
JPH01287976A (en) * 1988-05-13 1989-11-20 Sharp Corp Ceramic superconducting device
JPH01303767A (en) * 1988-05-31 1989-12-07 Sharp Corp Superconducting logical device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61143842A (en) * 1984-12-14 1986-07-01 アールシーエー　トムソン　ライセンシング　コーポレイシヨン Binary subtraction stage
JPH01287976A (en) * 1988-05-13 1989-11-20 Sharp Corp Ceramic superconducting device
JPH01303767A (en) * 1988-05-31 1989-12-07 Sharp Corp Superconducting logical device

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