JPS54127241A - Input-output control system - Google Patents

Input-output control system

Info

Publication number
JPS54127241A
JPS54127241A JP3517278A JP3517278A JPS54127241A JP S54127241 A JPS54127241 A JP S54127241A JP 3517278 A JP3517278 A JP 3517278A JP 3517278 A JP3517278 A JP 3517278A JP S54127241 A JPS54127241 A JP S54127241A
Authority
JP
Japan
Prior art keywords
bus
interface
control part
adaptor
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3517278A
Other languages
Japanese (ja)
Other versions
JPS581455B2 (en
Inventor
Shuji Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53035172A priority Critical patent/JPS581455B2/en
Publication of JPS54127241A publication Critical patent/JPS54127241A/en
Publication of JPS581455B2 publication Critical patent/JPS581455B2/en
Expired legal-status Critical Current

Links

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  • Bus Control (AREA)

Abstract

PURPOSE: To obtain an input-output control system which attains the address/length rewrite of DMA, without changing software and hardware, for an error recovery retry even if IOs are different in interface, at the time of connecting a different- interface IO device to one information system.
CONSTITUTION: An one of IO devices 13 of information processing system CPU11, adaptor unit 12 is connected to its bus 14 and a controller which controls the transfer of IO commands and interruptions from CPU11 to bus 15 and IO device 16 with an interface. Adaptor 21 is also an interface controller for the bus of one device controlled by a microcomputer and that of another one and composed of control part μCPU22 serving for the base body of the adaptor, ROM23 stored with firmware, RAM24 where commands from the CPU and an interrutpiton from an IO stand by, control part BCA25 which makes dialogue with the CPU, and bus control part BCB26 which makes bus dialogue with IOs.
COPYRIGHT: (C)1979,JPO&Japio
JP53035172A 1978-03-27 1978-03-27 Input/output control method Expired JPS581455B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53035172A JPS581455B2 (en) 1978-03-27 1978-03-27 Input/output control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53035172A JPS581455B2 (en) 1978-03-27 1978-03-27 Input/output control method

Publications (2)

Publication Number Publication Date
JPS54127241A true JPS54127241A (en) 1979-10-03
JPS581455B2 JPS581455B2 (en) 1983-01-11

Family

ID=12434430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53035172A Expired JPS581455B2 (en) 1978-03-27 1978-03-27 Input/output control method

Country Status (1)

Country Link
JP (1) JPS581455B2 (en)

Also Published As

Publication number Publication date
JPS581455B2 (en) 1983-01-11

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