JPS54127208A - Transmitter-receiver - Google Patents

Transmitter-receiver

Info

Publication number
JPS54127208A
JPS54127208A JP3415578A JP3415578A JPS54127208A JP S54127208 A JPS54127208 A JP S54127208A JP 3415578 A JP3415578 A JP 3415578A JP 3415578 A JP3415578 A JP 3415578A JP S54127208 A JPS54127208 A JP S54127208A
Authority
JP
Japan
Prior art keywords
switch
pass filter
frequency
transmitter
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3415578A
Other languages
Japanese (ja)
Other versions
JPS5722489B2 (en
Inventor
Masafumi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP3415578A priority Critical patent/JPS54127208A/en
Publication of JPS54127208A publication Critical patent/JPS54127208A/en
Publication of JPS5722489B2 publication Critical patent/JPS5722489B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Transmitters (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE: To simplify the constitution of a transmitter-receiver by using a switch for both inputting and outputting with the number of connection cables reduced.
CONSTITUTION: Since the intermediate frequency of an oridinary transmitter is equal to a frequency obtained by dividing an output frequency by an integer, low- pass filters 7a to 7c and high-pass filter 8 can be easily constituted by strip lines and miniaturized. Next, intermediate frequency fIF inputted to an input terminal is supplied to switch 3 via low-pass filter 7c. With switch 3 turned to the band- pass filter 5a side, the intermediate frequancy is applied to frequency converter 4a via low-pass filter 7a. The output frequency mixed with the oscillation frequency of local oscillator 6a is passed through switch 3 in an ON state and high-pass filter 8 and then outputted to terminal 2. Consequently, only one switch is required and the circuit constitution is simplified.
COPYRIGHT: (C)1979,JPO&Japio
JP3415578A 1978-03-27 1978-03-27 Transmitter-receiver Granted JPS54127208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3415578A JPS54127208A (en) 1978-03-27 1978-03-27 Transmitter-receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3415578A JPS54127208A (en) 1978-03-27 1978-03-27 Transmitter-receiver

Publications (2)

Publication Number Publication Date
JPS54127208A true JPS54127208A (en) 1979-10-03
JPS5722489B2 JPS5722489B2 (en) 1982-05-13

Family

ID=12406306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3415578A Granted JPS54127208A (en) 1978-03-27 1978-03-27 Transmitter-receiver

Country Status (1)

Country Link
JP (1) JPS54127208A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0336473Y2 (en) * 1986-06-30 1991-08-01

Also Published As

Publication number Publication date
JPS5722489B2 (en) 1982-05-13

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