JPS54120536A - Line texture generating circuit of display unit - Google Patents

Line texture generating circuit of display unit

Info

Publication number
JPS54120536A
JPS54120536A JP2813478A JP2813478A JPS54120536A JP S54120536 A JPS54120536 A JP S54120536A JP 2813478 A JP2813478 A JP 2813478A JP 2813478 A JP2813478 A JP 2813478A JP S54120536 A JPS54120536 A JP S54120536A
Authority
JP
Japan
Prior art keywords
circuit
line
data
signals
dda
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2813478A
Other languages
Japanese (ja)
Inventor
Tsuneo Ikedo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2813478A priority Critical patent/JPS54120536A/en
Publication of JPS54120536A publication Critical patent/JPS54120536A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to generate extremely many line patterns and to improve reliability by constituting a circuit easily by combining inexpensive logic elements, by obtaining sequential signals by allowing a DDA to compute picture data.
CONSTITUTION: In the process that sequential data are outputted from DDA (Digital Differential Analyzer) circuit 2, counter 10 of texture generating circuit 6 is advanced by X and Y axes increment and decrement signals (a) and (b) and repetitive operation at the address of ROM8 is done to supply write control circuit 3 with selected-9 one out of line pattern intermittent signals stored 8. Namely, if the signal from selector circuit 9 is "0", line data outputted are written into picture memory 4 and when "1", they are not under control 3; in this way, data stored in memory 4 are displayed by monitor circuit 5, so that a line will be drawn in an assigned line pattern.
COPYRIGHT: (C)1979,JPO&Japio
JP2813478A 1978-03-10 1978-03-10 Line texture generating circuit of display unit Pending JPS54120536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2813478A JPS54120536A (en) 1978-03-10 1978-03-10 Line texture generating circuit of display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2813478A JPS54120536A (en) 1978-03-10 1978-03-10 Line texture generating circuit of display unit

Publications (1)

Publication Number Publication Date
JPS54120536A true JPS54120536A (en) 1979-09-19

Family

ID=12240291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2813478A Pending JPS54120536A (en) 1978-03-10 1978-03-10 Line texture generating circuit of display unit

Country Status (1)

Country Link
JP (1) JPS54120536A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589194A (en) * 1981-07-10 1983-01-19 株式会社サイラック Color texture generation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589194A (en) * 1981-07-10 1983-01-19 株式会社サイラック Color texture generation circuit

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