JPS54113283A - Multiifunction circuit - Google Patents

Multiifunction circuit

Info

Publication number
JPS54113283A
JPS54113283A JP404379A JP404379A JPS54113283A JP S54113283 A JPS54113283 A JP S54113283A JP 404379 A JP404379 A JP 404379A JP 404379 A JP404379 A JP 404379A JP S54113283 A JPS54113283 A JP S54113283A
Authority
JP
Japan
Prior art keywords
multiifunction
circuit
multiifunction circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP404379A
Other languages
English (en)
Japanese (ja)
Inventor
Jiyorugensen Pieeru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bpifrance Financement SA
Original Assignee
Agence National de Valorisation de la Recherche ANVAR
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agence National de Valorisation de la Recherche ANVAR filed Critical Agence National de Valorisation de la Recherche ANVAR
Publication of JPS54113283A publication Critical patent/JPS54113283A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for multiplication or division
    • G06G7/163—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/04—Position modulation, i.e. PPM
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/06—Frequency or rate modulation, i.e. PFM or PRM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H10B99/10—Memory cells having a cross-point geometry

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Power Engineering (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Software Systems (AREA)
  • Mathematical Optimization (AREA)
  • Amplifiers (AREA)
  • Electronic Switches (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Amplitude Modulation (AREA)
JP404379A 1978-01-20 1979-01-19 Multiifunction circuit Pending JPS54113283A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7801600A FR2415392A1 (fr) 1978-01-20 1978-01-20 Circuit electronique multifonction a quatre circuits de base et applications de ce circuit

Publications (1)

Publication Number Publication Date
JPS54113283A true JPS54113283A (en) 1979-09-04

Family

ID=9203682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP404379A Pending JPS54113283A (en) 1978-01-20 1979-01-19 Multiifunction circuit

Country Status (5)

Country Link
JP (1) JPS54113283A (cg-RX-API-DMAC7.html)
DE (1) DE2902112A1 (cg-RX-API-DMAC7.html)
FR (1) FR2415392A1 (cg-RX-API-DMAC7.html)
GB (1) GB2015289B (cg-RX-API-DMAC7.html)
NL (1) NL7900398A (cg-RX-API-DMAC7.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59193627A (ja) * 1983-04-15 1984-11-02 Hitachi Ltd 半導体集積回路装置
JPS61186019A (ja) * 1985-02-13 1986-08-19 Toshiba Corp Ｅ↑２ｐｒｏｍ
JPH05242690A (ja) * 1992-06-19 1993-09-21 Toshiba Corp Ｅｅｐｒｏｍ

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3133518A1 (de) * 1981-08-25 1983-03-17 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt "elektronischer schalter"
GB2161044B (en) * 1984-06-28 1988-01-27 Stc Plc Telephone subscribers circuits
GB2228154B (en) * 1989-02-09 1993-04-21 Plessey Co Plc On-chip integrated oscillator circuits
US6803832B2 (en) 2002-09-06 2004-10-12 Freescale Semiconductor, Inc. Oscillator circuit having reduced layout area and lower power supply transients

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3694931A (en) * 1970-01-06 1972-10-03 Joseph J Bialek Training device for teaching digital logic operations

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59193627A (ja) * 1983-04-15 1984-11-02 Hitachi Ltd 半導体集積回路装置
JPS61186019A (ja) * 1985-02-13 1986-08-19 Toshiba Corp Ｅ↑２ｐｒｏｍ
JPH05242690A (ja) * 1992-06-19 1993-09-21 Toshiba Corp Ｅｅｐｒｏｍ

Also Published As

Publication number Publication date
FR2415392B1 (cg-RX-API-DMAC7.html) 1980-06-06
FR2415392A1 (fr) 1979-08-17
GB2015289A (en) 1979-09-05
GB2015289B (en) 1982-08-18
NL7900398A (nl) 1979-07-24
DE2902112A1 (de) 1979-09-06

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