JPS54104253A - Information processor - Google Patents

Information processor

Info

Publication number
JPS54104253A
JPS54104253A JP1048378A JP1048378A JPS54104253A JP S54104253 A JPS54104253 A JP S54104253A JP 1048378 A JP1048378 A JP 1048378A JP 1048378 A JP1048378 A JP 1048378A JP S54104253 A JPS54104253 A JP S54104253A
Authority
JP
Japan
Prior art keywords
address
access
processor
region
memory units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1048378A
Other languages
Japanese (ja)
Inventor
Keijirou Hayashi
Hiroaki Nakanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1048378A priority Critical patent/JPS54104253A/en
Publication of JPS54104253A publication Critical patent/JPS54104253A/en
Pending legal-status Critical Current

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Landscapes

  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

PURPOSE: To improve reliability and also to increase a degree of number of freedom for system operation by multiplied auxiliary memory units and a global memory unit which controls the whole system.
CONSTITUTION: Address widths of auxiliary memory units are denoted by (α), (β) and (γ). Processor 1 can attain access to access address (α+β) at its maximum. Processor 3 also has the maximum allowable address (α+β). Namely, although nothing seems available after (α+β), region (β) is exclusively used by processor 1 when processor 3 makes access to an address greater than (α), so that access to region (γ) will be attained by adding (β) to the access address without fail. Then, respective processes are executed actually while memories are used in common apparently. Processors can therefore be operated independently while the multiplication is stopped.
COPYRIGHT: (C)1979,JPO&Japio
JP1048378A 1978-02-03 1978-02-03 Information processor Pending JPS54104253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1048378A JPS54104253A (en) 1978-02-03 1978-02-03 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1048378A JPS54104253A (en) 1978-02-03 1978-02-03 Information processor

Publications (1)

Publication Number Publication Date
JPS54104253A true JPS54104253A (en) 1979-08-16

Family

ID=11751402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1048378A Pending JPS54104253A (en) 1978-02-03 1978-02-03 Information processor

Country Status (1)

Country Link
JP (1) JPS54104253A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS499938A (en) * 1972-03-31 1974-01-29
JPS5024046A (en) * 1973-07-04 1975-03-14

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS499938A (en) * 1972-03-31 1974-01-29
JPS5024046A (en) * 1973-07-04 1975-03-14

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