JPS5384649A - Multilevel logic circuit - Google Patents

Multilevel logic circuit

Info

Publication number
JPS5384649A
JPS5384649A JP16064076A JP16064076A JPS5384649A JP S5384649 A JPS5384649 A JP S5384649A JP 16064076 A JP16064076 A JP 16064076A JP 16064076 A JP16064076 A JP 16064076A JP S5384649 A JPS5384649 A JP S5384649A
Authority
JP
Japan
Prior art keywords
logic circuit
multilevel logic
multilevel
fet
simplify
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16064076A
Other languages
Japanese (ja)
Other versions
JPS576852B2 (en
Inventor
Katsuhiko Suyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16064076A priority Critical patent/JPS5384649A/en
Publication of JPS5384649A publication Critical patent/JPS5384649A/en
Publication of JPS576852B2 publication Critical patent/JPS576852B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To simplify the circuit constitution by connecting a plural number of non-linear loads to one FET or bipolar transistor.
JP16064076A 1976-12-29 1976-12-29 Multilevel logic circuit Granted JPS5384649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16064076A JPS5384649A (en) 1976-12-29 1976-12-29 Multilevel logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16064076A JPS5384649A (en) 1976-12-29 1976-12-29 Multilevel logic circuit

Publications (2)

Publication Number Publication Date
JPS5384649A true JPS5384649A (en) 1978-07-26
JPS576852B2 JPS576852B2 (en) 1982-02-06

Family

ID=15719292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16064076A Granted JPS5384649A (en) 1976-12-29 1976-12-29 Multilevel logic circuit

Country Status (1)

Country Link
JP (1) JPS5384649A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938061A (en) * 1972-08-25 1974-04-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938061A (en) * 1972-08-25 1974-04-09

Also Published As

Publication number Publication date
JPS576852B2 (en) 1982-02-06

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