JPS537770B2 - - Google Patents

Info

Publication number
JPS537770B2
JPS537770B2 JP3310875A JP3310875A JPS537770B2 JP S537770 B2 JPS537770 B2 JP S537770B2 JP 3310875 A JP3310875 A JP 3310875A JP 3310875 A JP3310875 A JP 3310875A JP S537770 B2 JPS537770 B2 JP S537770B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3310875A
Other versions
JPS50159941A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS50159941A publication Critical patent/JPS50159941A/ja
Publication of JPS537770B2 publication Critical patent/JPS537770B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/764—Masking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
JP3310875A 1974-06-03 1975-03-20 Expired JPS537770B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US475533A US3906459A (en) 1974-06-03 1974-06-03 Binary data manipulation network having multiple function capability for computers

Publications (2)

Publication Number Publication Date
JPS50159941A JPS50159941A (ja) 1975-12-24
JPS537770B2 true JPS537770B2 (ja) 1978-03-22

Family

ID=23888000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3310875A Expired JPS537770B2 (ja) 1974-06-03 1975-03-20

Country Status (7)

Country Link
US (1) US3906459A (ja)
JP (1) JPS537770B2 (ja)
CA (1) CA1005924A (ja)
DE (1) DE2506671C3 (ja)
FR (1) FR2275825A1 (ja)
GB (1) GB1475962A (ja)
NL (1) NL172798C (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4139899A (en) * 1976-10-18 1979-02-13 Burroughs Corporation Shift network having a mask generator and a rotator
US4194241A (en) * 1977-07-08 1980-03-18 Xerox Corporation Bit manipulation circuitry in a microprocessor
US4219874A (en) * 1978-03-17 1980-08-26 Gusev Valery Data processing device for variable length multibyte data fields
US4180861A (en) * 1978-03-31 1979-12-25 Ncr Corporation Selectively operable mask generator
US4569016A (en) * 1983-06-30 1986-02-04 International Business Machines Corporation Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
JPS6476220A (en) * 1987-09-17 1989-03-22 Ibm Bit mask generation circuit
US5410719A (en) * 1992-05-27 1995-04-25 Hewlett-Packard Company Field compositor for merging data and including cells each receiving three control and two data inputs and generating one control and one data output therefrom
US5487159A (en) * 1993-12-23 1996-01-23 Unisys Corporation System for processing shift, mask, and merge operations in one instruction
US6061783A (en) * 1996-11-13 2000-05-09 Nortel Networks Corporation Method and apparatus for manipulation of bit fields directly in a memory source
US20030231660A1 (en) * 2002-06-14 2003-12-18 Bapiraju Vinnakota Bit-manipulation instructions for packet processing
US20040254966A1 (en) * 2003-05-16 2004-12-16 Daewoo Educational Foundation Bit manipulation operation circuit and method in programmable processor
KR20070088190A (ko) * 2006-02-24 2007-08-29 삼성전자주식회사 멀티미디어 데이터 처리를 위한 서브워드 병렬 처리 방법
FR3101981B1 (fr) * 2019-10-11 2021-11-12 St Microelectronics Grenoble 2 Extraction et insertion de mots binaires

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3430202A (en) * 1964-10-07 1969-02-25 Bell Telephone Labor Inc Data processor utilizing combined order instructions
US3343138A (en) * 1964-10-07 1967-09-19 Bell Telephone Labor Inc Data processor employing double indexing
US3370274A (en) * 1964-12-30 1968-02-20 Bell Telephone Labor Inc Data processor control utilizing tandem signal operations
US3387278A (en) * 1965-10-20 1968-06-04 Bell Telephone Labor Inc Data processor with simultaneous testing and indexing on conditional transfer operations

Also Published As

Publication number Publication date
AU8153975A (en) 1976-12-02
JPS50159941A (ja) 1975-12-24
DE2506671C3 (de) 1981-01-15
NL172798B (nl) 1983-05-16
DE2506671A1 (de) 1975-12-11
DE2506671B2 (de) 1980-04-30
FR2275825A1 (fr) 1976-01-16
GB1475962A (en) 1977-06-10
NL7506503A (nl) 1975-12-05
CA1005924A (en) 1977-02-22
US3906459A (en) 1975-09-16
FR2275825B1 (ja) 1977-12-02
NL172798C (nl) 1983-10-17

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