JPS5367327A - Bit processor - Google Patents

Bit processor

Info

Publication number
JPS5367327A
JPS5367327A JP14272576A JP14272576A JPS5367327A JP S5367327 A JPS5367327 A JP S5367327A JP 14272576 A JP14272576 A JP 14272576A JP 14272576 A JP14272576 A JP 14272576A JP S5367327 A JPS5367327 A JP S5367327A
Authority
JP
Japan
Prior art keywords
bit processor
logic
writing
rom
enable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14272576A
Other languages
Japanese (ja)
Inventor
Takeshi Tokuda
Mitsuo Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14272576A priority Critical patent/JPS5367327A/en
Publication of JPS5367327A publication Critical patent/JPS5367327A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To enable a standard LSI formation for the hard wired logic by producing a program corresponding to the logic and writing it into ROM.
JP14272576A 1976-11-27 1976-11-27 Bit processor Pending JPS5367327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14272576A JPS5367327A (en) 1976-11-27 1976-11-27 Bit processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14272576A JPS5367327A (en) 1976-11-27 1976-11-27 Bit processor

Publications (1)

Publication Number Publication Date
JPS5367327A true JPS5367327A (en) 1978-06-15

Family

ID=15322123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14272576A Pending JPS5367327A (en) 1976-11-27 1976-11-27 Bit processor

Country Status (1)

Country Link
JP (1) JPS5367327A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5543612A (en) * 1978-09-22 1980-03-27 Hitachi Ltd Logic arithmetic unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5543612A (en) * 1978-09-22 1980-03-27 Hitachi Ltd Logic arithmetic unit

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