JPS5365766A - Input offset voltage measuring method for semiconductive integrated linear circuit - Google Patents
Input offset voltage measuring method for semiconductive integrated linear circuitInfo
- Publication number
- JPS5365766A JPS5365766A JP14085876A JP14085876A JPS5365766A JP S5365766 A JPS5365766 A JP S5365766A JP 14085876 A JP14085876 A JP 14085876A JP 14085876 A JP14085876 A JP 14085876A JP S5365766 A JPS5365766 A JP S5365766A
- Authority
- JP
- Japan
- Prior art keywords
- offset voltage
- input offset
- measuring method
- voltage measuring
- linear circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Measurement Of Resistance Or Impedance (AREA)
Abstract
PURPOSE: To measure the input offset voltage with a stability and high accuracy, by carrying out positive feedback to the body to be measured, without generating the oscillation, even when broad band operational amplifier etc., is applied to the body to be measured.
COPYRIGHT: (C)1978,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51140858A JPS5931011B2 (en) | 1976-11-22 | 1976-11-22 | Method for measuring input offset voltage of semiconductor integrated linear circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51140858A JPS5931011B2 (en) | 1976-11-22 | 1976-11-22 | Method for measuring input offset voltage of semiconductor integrated linear circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5365766A true JPS5365766A (en) | 1978-06-12 |
JPS5931011B2 JPS5931011B2 (en) | 1984-07-30 |
Family
ID=15278367
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51140858A Expired JPS5931011B2 (en) | 1976-11-22 | 1976-11-22 | Method for measuring input offset voltage of semiconductor integrated linear circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5931011B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6611302B1 (en) | 1999-07-14 | 2003-08-26 | Nec Lcd Technologies, Ltd. | Flat panel display device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63148823U (en) * | 1987-03-19 | 1988-09-30 |
-
1976
- 1976-11-22 JP JP51140858A patent/JPS5931011B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6611302B1 (en) | 1999-07-14 | 2003-08-26 | Nec Lcd Technologies, Ltd. | Flat panel display device |
Also Published As
Publication number | Publication date |
---|---|
JPS5931011B2 (en) | 1984-07-30 |
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