JPS5363869A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5363869A
JPS5363869A JP13879776A JP13879776A JPS5363869A JP S5363869 A JPS5363869 A JP S5363869A JP 13879776 A JP13879776 A JP 13879776A JP 13879776 A JP13879776 A JP 13879776A JP S5363869 A JPS5363869 A JP S5363869A
Authority
JP
Japan
Prior art keywords
semiconductor device
solder
pads
cover
support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13879776A
Other languages
Japanese (ja)
Inventor
Koichi Oguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP13879776A priority Critical patent/JPS5363869A/en
Publication of JPS5363869A publication Critical patent/JPS5363869A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To cover the lead ends of and IC support with solder and bond tape carriers directly to Al pads.
JP13879776A 1976-11-18 1976-11-18 Semiconductor device Pending JPS5363869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13879776A JPS5363869A (en) 1976-11-18 1976-11-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13879776A JPS5363869A (en) 1976-11-18 1976-11-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5363869A true JPS5363869A (en) 1978-06-07

Family

ID=15230441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13879776A Pending JPS5363869A (en) 1976-11-18 1976-11-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5363869A (en)

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