JPS5362953A - Test method for logical device - Google Patents

Test method for logical device

Info

Publication number
JPS5362953A
JPS5362953A JP13820376A JP13820376A JPS5362953A JP S5362953 A JPS5362953 A JP S5362953A JP 13820376 A JP13820376 A JP 13820376A JP 13820376 A JP13820376 A JP 13820376A JP S5362953 A JPS5362953 A JP S5362953A
Authority
JP
Japan
Prior art keywords
test method
scan
logical device
circuit
redundancy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13820376A
Other languages
Japanese (ja)
Other versions
JPS5646173B2 (en
Inventor
Seijiro Ueno
Koji Hashiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13820376A priority Critical patent/JPS5362953A/en
Publication of JPS5362953A publication Critical patent/JPS5362953A/en
Publication of JPS5646173B2 publication Critical patent/JPS5646173B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To lower the redundancy by securing a circuit constitution in such a way that the address decoder part, scan-in circuit and scan-out circuit are formed into nearly a unit. As a result, the scan-in and scan-out can be realized.
COPYRIGHT: (C)1978,JPO&Japio
JP13820376A 1976-11-17 1976-11-17 Test method for logical device Granted JPS5362953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13820376A JPS5362953A (en) 1976-11-17 1976-11-17 Test method for logical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13820376A JPS5362953A (en) 1976-11-17 1976-11-17 Test method for logical device

Publications (2)

Publication Number Publication Date
JPS5362953A true JPS5362953A (en) 1978-06-05
JPS5646173B2 JPS5646173B2 (en) 1981-10-31

Family

ID=15216481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13820376A Granted JPS5362953A (en) 1976-11-17 1976-11-17 Test method for logical device

Country Status (1)

Country Link
JP (1) JPS5362953A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946247A (en) * 1994-05-26 1999-08-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory testing device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60112072U (en) * 1984-01-06 1985-07-29 富士電気化学株式会社 thin battery

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946247A (en) * 1994-05-26 1999-08-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory testing device

Also Published As

Publication number Publication date
JPS5646173B2 (en) 1981-10-31

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