JPS5356913A - Clock phase synchronous circuit - Google Patents

Clock phase synchronous circuit

Info

Publication number
JPS5356913A
JPS5356913A JP13205876A JP13205876A JPS5356913A JP S5356913 A JPS5356913 A JP S5356913A JP 13205876 A JP13205876 A JP 13205876A JP 13205876 A JP13205876 A JP 13205876A JP S5356913 A JPS5356913 A JP S5356913A
Authority
JP
Japan
Prior art keywords
phase synchronous
clock phase
synchronous circuit
synchronous loop
multiplexing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13205876A
Other languages
Japanese (ja)
Other versions
JPS6019175B2 (en
Inventor
Kazuo Iguchi
Kyoji Kameo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP51132058A priority Critical patent/JPS6019175B2/en
Publication of JPS5356913A publication Critical patent/JPS5356913A/en
Publication of JPS6019175B2 publication Critical patent/JPS6019175B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To make it possible to continue a synchronizing function with triggering automatically a phase synchronous loop when the operation of a pulse generator stops, by providing a logical oscillator in the phase synchronous loop in multiplexing of PCM signals.
JP51132058A 1976-11-02 1976-11-02 Clock phase synchronization circuit Expired JPS6019175B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51132058A JPS6019175B2 (en) 1976-11-02 1976-11-02 Clock phase synchronization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51132058A JPS6019175B2 (en) 1976-11-02 1976-11-02 Clock phase synchronization circuit

Publications (2)

Publication Number Publication Date
JPS5356913A true JPS5356913A (en) 1978-05-23
JPS6019175B2 JPS6019175B2 (en) 1985-05-15

Family

ID=15072523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51132058A Expired JPS6019175B2 (en) 1976-11-02 1976-11-02 Clock phase synchronization circuit

Country Status (1)

Country Link
JP (1) JPS6019175B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170831A (en) * 1984-08-29 1986-04-11 バロース・コーポレーシヨン Automatic signal delay regulator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170831A (en) * 1984-08-29 1986-04-11 バロース・コーポレーシヨン Automatic signal delay regulator
JPH0431451B2 (en) * 1984-08-29 1992-05-26

Also Published As

Publication number Publication date
JPS6019175B2 (en) 1985-05-15

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