JPS5352045Y2 - - Google Patents
Info
- Publication number
- JPS5352045Y2 JPS5352045Y2 JP1976148498U JP14849876U JPS5352045Y2 JP S5352045 Y2 JPS5352045 Y2 JP S5352045Y2 JP 1976148498 U JP1976148498 U JP 1976148498U JP 14849876 U JP14849876 U JP 14849876U JP S5352045 Y2 JPS5352045 Y2 JP S5352045Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Multi-Conductor Connections (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976148498U JPS5352045Y2 (en:Method) | 1976-11-04 | 1976-11-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976148498U JPS5352045Y2 (en:Method) | 1976-11-04 | 1976-11-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5276944U JPS5276944U (en:Method) | 1977-06-08 |
| JPS5352045Y2 true JPS5352045Y2 (en:Method) | 1978-12-12 |
Family
ID=28628042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1976148498U Expired JPS5352045Y2 (en:Method) | 1976-11-04 | 1976-11-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5352045Y2 (en:Method) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3312878A (en) * | 1965-06-01 | 1967-04-04 | Ibm | High speed packaging of miniaturized circuit modules |
-
1976
- 1976-11-04 JP JP1976148498U patent/JPS5352045Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5276944U (en:Method) | 1977-06-08 |