JPS5335435A - Automatic tlb erase and processing unit - Google Patents

Automatic tlb erase and processing unit

Info

Publication number
JPS5335435A
JPS5335435A JP11030976A JP11030976A JPS5335435A JP S5335435 A JPS5335435 A JP S5335435A JP 11030976 A JP11030976 A JP 11030976A JP 11030976 A JP11030976 A JP 11030976A JP S5335435 A JPS5335435 A JP S5335435A
Authority
JP
Japan
Prior art keywords
tlb
erase
automatic
processing unit
conversion table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11030976A
Other languages
Japanese (ja)
Inventor
Takashi Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11030976A priority Critical patent/JPS5335435A/en
Publication of JPS5335435A publication Critical patent/JPS5335435A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To perform the ineffective processing easily, by referencing the second conversion table and making ineffective the conversion of the page logic address versus page real address on the first conversion table.
JP11030976A 1976-09-14 1976-09-14 Automatic tlb erase and processing unit Pending JPS5335435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11030976A JPS5335435A (en) 1976-09-14 1976-09-14 Automatic tlb erase and processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11030976A JPS5335435A (en) 1976-09-14 1976-09-14 Automatic tlb erase and processing unit

Publications (1)

Publication Number Publication Date
JPS5335435A true JPS5335435A (en) 1978-04-01

Family

ID=14532431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11030976A Pending JPS5335435A (en) 1976-09-14 1976-09-14 Automatic tlb erase and processing unit

Country Status (1)

Country Link
JP (1) JPS5335435A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10386889B2 (en) 2013-12-11 2019-08-20 Apple Inc. Cover glass for an electronic device
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10386889B2 (en) 2013-12-11 2019-08-20 Apple Inc. Cover glass for an electronic device
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components

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