JPS533134A - Timing generation method for memory - Google Patents

Timing generation method for memory

Info

Publication number
JPS533134A
JPS533134A JP7658076A JP7658076A JPS533134A JP S533134 A JPS533134 A JP S533134A JP 7658076 A JP7658076 A JP 7658076A JP 7658076 A JP7658076 A JP 7658076A JP S533134 A JPS533134 A JP S533134A
Authority
JP
Japan
Prior art keywords
memory
generation method
timing generation
enhance
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7658076A
Other languages
Japanese (ja)
Other versions
JPS5719502B2 (en
Inventor
Hitoshi Sato
Yoshio Nakano
Tadashi Kawanobe
Nobuo Muto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7658076A priority Critical patent/JPS533134A/en
Publication of JPS533134A publication Critical patent/JPS533134A/en
Publication of JPS5719502B2 publication Critical patent/JPS5719502B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To enhance the cost performance by generating a timing suitable for the memory card through an automatic switching for the memory using IC memory.
JP7658076A 1976-06-30 1976-06-30 Timing generation method for memory Granted JPS533134A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7658076A JPS533134A (en) 1976-06-30 1976-06-30 Timing generation method for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7658076A JPS533134A (en) 1976-06-30 1976-06-30 Timing generation method for memory

Publications (2)

Publication Number Publication Date
JPS533134A true JPS533134A (en) 1978-01-12
JPS5719502B2 JPS5719502B2 (en) 1982-04-22

Family

ID=13609200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7658076A Granted JPS533134A (en) 1976-06-30 1976-06-30 Timing generation method for memory

Country Status (1)

Country Link
JP (1) JPS533134A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58139228A (en) * 1982-02-10 1983-08-18 Nec Corp Controlling system of interface of peripheral device
JPS61180990A (en) * 1985-10-25 1986-08-13 Nec Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58139228A (en) * 1982-02-10 1983-08-18 Nec Corp Controlling system of interface of peripheral device
JPS61180990A (en) * 1985-10-25 1986-08-13 Nec Corp Semiconductor device
JPS6237471B2 (en) * 1985-10-25 1987-08-12 Nippon Electric Co

Also Published As

Publication number Publication date
JPS5719502B2 (en) 1982-04-22

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