JPS58139228A - Controlling system of interface of peripheral device - Google Patents

Controlling system of interface of peripheral device

Info

Publication number
JPS58139228A
JPS58139228A JP1990582A JP1990582A JPS58139228A JP S58139228 A JPS58139228 A JP S58139228A JP 1990582 A JP1990582 A JP 1990582A JP 1990582 A JP1990582 A JP 1990582A JP S58139228 A JPS58139228 A JP S58139228A
Authority
JP
Japan
Prior art keywords
peripheral device
signal
signal line
turns
controlling part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990582A
Other languages
Japanese (ja)
Inventor
Yuji Takeya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1990582A priority Critical patent/JPS58139228A/en
Publication of JPS58139228A publication Critical patent/JPS58139228A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Abstract

PURPOSE:To reduce physical quantity by using a connector in common when a peripheral device is to be connected to a peripheral device controlling part and also using a logical circuit in common without changing the connector connecting position of each peripheral device. CONSTITUTION:When the peripheral device controlling part 2 turns off a signal (d) of an interface signal line 7 after sending data (g) to a data line 18, the peripheral device 17 turns on a signal (e) of a signal line 12 and enters the data (g). After detecting the on state of the signal (e) on the signal line 12, the controlling part 2 turns on a signal (d) of a signal line 7 to end one data transfer. When the succeeding data input is ready after completing the processing of the input signal (g), the peripheral device 17 turns off the signal (e) on the signal line 12. After detecting the off state of the signal (e) on the signal line 12, the peripheral device controlling part 2 starts the succeeding data transfer.
JP1990582A 1982-02-10 1982-02-10 Controlling system of interface of peripheral device Pending JPS58139228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990582A JPS58139228A (en) 1982-02-10 1982-02-10 Controlling system of interface of peripheral device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990582A JPS58139228A (en) 1982-02-10 1982-02-10 Controlling system of interface of peripheral device

Publications (1)

Publication Number Publication Date
JPS58139228A true JPS58139228A (en) 1983-08-18

Family

ID=12012224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990582A Pending JPS58139228A (en) 1982-02-10 1982-02-10 Controlling system of interface of peripheral device

Country Status (1)

Country Link
JP (1) JPS58139228A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH056238A (en) * 1991-06-26 1993-01-14 Nisca Corp Signal processor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5219925A (en) * 1975-08-08 1977-02-15 Mitsubishi Electric Corp Memory unit
JPS533134A (en) * 1976-06-30 1978-01-12 Nec Corp Timing generation method for memory
JPS5676822A (en) * 1979-11-27 1981-06-24 Ricoh Co Ltd Control system for input/output device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5219925A (en) * 1975-08-08 1977-02-15 Mitsubishi Electric Corp Memory unit
JPS533134A (en) * 1976-06-30 1978-01-12 Nec Corp Timing generation method for memory
JPS5676822A (en) * 1979-11-27 1981-06-24 Ricoh Co Ltd Control system for input/output device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH056238A (en) * 1991-06-26 1993-01-14 Nisca Corp Signal processor

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