JPS5325736B2 - - Google Patents
Info
- Publication number
- JPS5325736B2 JPS5325736B2 JP8594673A JP8594673A JPS5325736B2 JP S5325736 B2 JPS5325736 B2 JP S5325736B2 JP 8594673 A JP8594673 A JP 8594673A JP 8594673 A JP8594673 A JP 8594673A JP S5325736 B2 JPS5325736 B2 JP S5325736B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
- H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronizing For Television (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8594673A JPS5325736B2 (fr) | 1973-07-31 | 1973-07-31 | |
| DE2436711A DE2436711A1 (de) | 1973-07-31 | 1974-07-30 | Automatischer horizontalfrequenz-regler |
| BR624974A BR7406249D0 (pt) | 1973-07-31 | 1974-07-30 | Circuitos de controle de frequencia horizontal automatico |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8594673A JPS5325736B2 (fr) | 1973-07-31 | 1973-07-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5034408A JPS5034408A (fr) | 1975-04-02 |
| JPS5325736B2 true JPS5325736B2 (fr) | 1978-07-28 |
Family
ID=13872916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8594673A Expired JPS5325736B2 (fr) | 1973-07-31 | 1973-07-31 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS5325736B2 (fr) |
| BR (1) | BR7406249D0 (fr) |
| DE (1) | DE2436711A1 (fr) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5250714U (fr) * | 1975-10-09 | 1977-04-11 | ||
| JPH0528850Y2 (fr) * | 1987-02-18 | 1993-07-23 | ||
| JP2628757B2 (ja) * | 1989-07-31 | 1997-07-09 | シャープ株式会社 | フェイズロックドループ発振回路 |
| US6703893B1 (en) * | 2002-11-25 | 2004-03-09 | Intersil Americas Inc. | Method of setting bi-directional offset in a PWM controller using a single programming pin |
-
1973
- 1973-07-31 JP JP8594673A patent/JPS5325736B2/ja not_active Expired
-
1974
- 1974-07-30 DE DE2436711A patent/DE2436711A1/de active Pending
- 1974-07-30 BR BR624974A patent/BR7406249D0/pt unknown
Also Published As
| Publication number | Publication date |
|---|---|
| DE2436711A1 (de) | 1975-02-27 |
| BR7406249D0 (pt) | 1975-05-13 |
| JPS5034408A (fr) | 1975-04-02 |