JPS5317457B2 - - Google Patents
Info
- Publication number
- JPS5317457B2 JPS5317457B2 JP12410173A JP12410173A JPS5317457B2 JP S5317457 B2 JPS5317457 B2 JP S5317457B2 JP 12410173 A JP12410173 A JP 12410173A JP 12410173 A JP12410173 A JP 12410173A JP S5317457 B2 JPS5317457 B2 JP S5317457B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6028—Prefetching based on hints or prefetch instructions
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US00312551A US3839704A (en) | 1972-12-06 | 1972-12-06 | Control for channel access to storage hierarchy system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4989448A JPS4989448A (US20110009641A1-20110113-C00256.png) | 1974-08-27 |
| JPS5317457B2 true JPS5317457B2 (US20110009641A1-20110113-C00256.png) | 1978-06-08 |
Family
ID=23211983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12410173A Expired JPS5317457B2 (US20110009641A1-20110113-C00256.png) | 1972-12-06 | 1973-11-06 |
Country Status (6)
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5816263B2 (ja) * | 1975-11-28 | 1983-03-30 | 株式会社日立製作所 | ジヨウホウシヨリソウチ |
| DE2853501A1 (de) * | 1978-12-12 | 1980-06-26 | Ibm Deutschland | Speicherhierarchie mit ladungsverschiebungsspeicher |
| US4442488A (en) * | 1980-05-05 | 1984-04-10 | Floating Point Systems, Inc. | Instruction cache memory system |
| US4571674A (en) * | 1982-09-27 | 1986-02-18 | International Business Machines Corporation | Peripheral storage system having multiple data transfer rates |
| US11307773B1 (en) | 2018-05-02 | 2022-04-19 | Innovium, Inc. | Memory-based power stabilization in a network device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3533075A (en) * | 1967-10-19 | 1970-10-06 | Ibm | Dynamic address translation unit with look-ahead |
| US3569938A (en) * | 1967-12-20 | 1971-03-09 | Ibm | Storage manager |
| US3588829A (en) * | 1968-11-14 | 1971-06-28 | Ibm | Integrated memory system with block transfer to a buffer store |
| US3670309A (en) * | 1969-12-23 | 1972-06-13 | Ibm | Storage control system |
| US3647348A (en) * | 1970-01-19 | 1972-03-07 | Fairchild Camera Instr Co | Hardware-oriented paging control system |
| CA954232A (en) * | 1970-06-15 | 1974-09-03 | International Business Machines Corporation | Channel-memory bus control |
| FR10582E (fr) * | 1970-06-29 | 1909-07-30 | Paul Alexis Victor Lerolle | Jeu de serrures avec passe-partout |
| US3693165A (en) * | 1971-06-29 | 1972-09-19 | Ibm | Parallel addressing of a storage hierarchy in a data processing system using virtual addressing |
-
1972
- 1972-12-06 US US00312551A patent/US3839704A/en not_active Expired - Lifetime
-
1973
- 1973-10-04 GB GB4630873A patent/GB1400353A/en not_active Expired
- 1973-10-17 IT IT30207/73A patent/IT1001595B/it active
- 1973-10-29 FR FR7339436A patent/FR2212959A5/fr not_active Expired
- 1973-11-06 JP JP12410173A patent/JPS5317457B2/ja not_active Expired
- 1973-11-08 DE DE2355814A patent/DE2355814C2/de not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US3839704A (en) | 1974-10-01 |
| JPS4989448A (US20110009641A1-20110113-C00256.png) | 1974-08-27 |
| DE2355814A1 (de) | 1974-06-12 |
| IT1001595B (it) | 1976-04-30 |
| GB1400353A (en) | 1975-07-16 |
| FR2212959A5 (US20110009641A1-20110113-C00256.png) | 1974-07-26 |
| DE2355814C2 (de) | 1984-06-28 |
