CA954232A - Channel-memory bus control - Google Patents
Channel-memory bus controlInfo
- Publication number
- CA954232A CA954232A CA109,036A CA109036A CA954232A CA 954232 A CA954232 A CA 954232A CA 109036 A CA109036 A CA 109036A CA 954232 A CA954232 A CA 954232A
- Authority
- CA
- Canada
- Prior art keywords
- channel
- memory bus
- bus control
- control
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US4608170A | 1970-06-15 | 1970-06-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA954232A true CA954232A (en) | 1974-09-03 |
Family
ID=21941501
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA109,036A Expired CA954232A (en) | 1970-06-15 | 1971-03-30 | Channel-memory bus control |
Country Status (8)
Country | Link |
---|---|
JP (1) | JPS505009B1 (en) |
BE (1) | BE767625A (en) |
CA (1) | CA954232A (en) |
DE (1) | DE2129268C3 (en) |
FR (1) | FR2095546A5 (en) |
GB (1) | GB1340382A (en) |
NL (1) | NL7108230A (en) |
SE (1) | SE365628B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3839704A (en) * | 1972-12-06 | 1974-10-01 | Ibm | Control for channel access to storage hierarchy system |
-
1971
- 1971-03-30 CA CA109,036A patent/CA954232A/en not_active Expired
- 1971-04-29 FR FR7116460A patent/FR2095546A5/fr not_active Expired
- 1971-05-11 GB GB1419171A patent/GB1340382A/en not_active Expired
- 1971-05-25 JP JP3522471A patent/JPS505009B1/ja active Pending
- 1971-05-25 BE BE767625A patent/BE767625A/en unknown
- 1971-06-12 DE DE19712129268 patent/DE2129268C3/en not_active Expired
- 1971-06-15 NL NL7108230A patent/NL7108230A/xx active Search and Examination
- 1971-06-15 SE SE07753/71A patent/SE365628B/xx unknown
Also Published As
Publication number | Publication date |
---|---|
JPS505009B1 (en) | 1975-02-27 |
NL7108230A (en) | 1971-12-17 |
FR2095546A5 (en) | 1972-02-11 |
BE767625A (en) | 1971-10-18 |
SE365628B (en) | 1974-03-25 |
GB1340382A (en) | 1973-12-12 |
DE2129268C3 (en) | 1981-01-22 |
DE2129268A1 (en) | 1971-12-30 |
DE2129268B2 (en) | 1980-05-08 |
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