JPS53116007A - Data transfer system in competition - Google Patents

Data transfer system in competition

Info

Publication number
JPS53116007A
JPS53116007A JP3072177A JP3072177A JPS53116007A JP S53116007 A JPS53116007 A JP S53116007A JP 3072177 A JP3072177 A JP 3072177A JP 3072177 A JP3072177 A JP 3072177A JP S53116007 A JPS53116007 A JP S53116007A
Authority
JP
Japan
Prior art keywords
competition
data transfer
transfer system
malfuction
clocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3072177A
Other languages
Japanese (ja)
Other versions
JPS572238B2 (en
Inventor
Toru Tejima
Kiyoshi Kitagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3072177A priority Critical patent/JPS53116007A/en
Publication of JPS53116007A publication Critical patent/JPS53116007A/en
Publication of JPS572238B2 publication Critical patent/JPS572238B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To avoid malfuction to instructions from two sets of controllers simultaneously, by using clocks having the different phase in the data buffer of an electronic exchanger.
JP3072177A 1977-03-19 1977-03-19 Data transfer system in competition Granted JPS53116007A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3072177A JPS53116007A (en) 1977-03-19 1977-03-19 Data transfer system in competition

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3072177A JPS53116007A (en) 1977-03-19 1977-03-19 Data transfer system in competition

Publications (2)

Publication Number Publication Date
JPS53116007A true JPS53116007A (en) 1978-10-11
JPS572238B2 JPS572238B2 (en) 1982-01-14

Family

ID=12311501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3072177A Granted JPS53116007A (en) 1977-03-19 1977-03-19 Data transfer system in competition

Country Status (1)

Country Link
JP (1) JPS53116007A (en)

Also Published As

Publication number Publication date
JPS572238B2 (en) 1982-01-14

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