JPS53111249A - Refresh control circuit for dynamic memory - Google Patents

Refresh control circuit for dynamic memory

Info

Publication number
JPS53111249A
JPS53111249A JP1922877A JP1922877A JPS53111249A JP S53111249 A JPS53111249 A JP S53111249A JP 1922877 A JP1922877 A JP 1922877A JP 1922877 A JP1922877 A JP 1922877A JP S53111249 A JPS53111249 A JP S53111249A
Authority
JP
Japan
Prior art keywords
control circuit
dynamic memory
memory
refresh control
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1922877A
Other languages
English (en)
Inventor
Shigeshiro Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1922877A priority Critical patent/JPS53111249A/ja
Publication of JPS53111249A publication Critical patent/JPS53111249A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
JP1922877A 1977-02-25 1977-02-25 Refresh control circuit for dynamic memory Pending JPS53111249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1922877A JPS53111249A (en) 1977-02-25 1977-02-25 Refresh control circuit for dynamic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1922877A JPS53111249A (en) 1977-02-25 1977-02-25 Refresh control circuit for dynamic memory

Publications (1)

Publication Number Publication Date
JPS53111249A true JPS53111249A (en) 1978-09-28

Family

ID=11993508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1922877A Pending JPS53111249A (en) 1977-02-25 1977-02-25 Refresh control circuit for dynamic memory

Country Status (1)

Country Link
JP (1) JPS53111249A (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010928A (ja) * 1973-05-28 1975-02-04
JPS50102232A (ja) * 1974-01-09 1975-08-13
JPS50105340A (ja) * 1974-01-25 1975-08-20

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010928A (ja) * 1973-05-28 1975-02-04
JPS50102232A (ja) * 1974-01-09 1975-08-13
JPS50105340A (ja) * 1974-01-25 1975-08-20

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