JPS53106672U - - Google Patents

Info

Publication number
JPS53106672U
JPS53106672U JP1977011376U JP1137677U JPS53106672U JP S53106672 U JPS53106672 U JP S53106672U JP 1977011376 U JP1977011376 U JP 1977011376U JP 1137677 U JP1137677 U JP 1137677U JP S53106672 U JPS53106672 U JP S53106672U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1977011376U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1977011376U priority Critical patent/JPS53106672U/ja
Publication of JPS53106672U publication Critical patent/JPS53106672U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1977011376U 1977-02-01 1977-02-01 Pending JPS53106672U (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1977011376U JPS53106672U (enExample) 1977-02-01 1977-02-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977011376U JPS53106672U (enExample) 1977-02-01 1977-02-01

Publications (1)

Publication Number Publication Date
JPS53106672U true JPS53106672U (enExample) 1978-08-26

Family

ID=28825686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1977011376U Pending JPS53106672U (enExample) 1977-02-01 1977-02-01

Country Status (1)

Country Link
JP (1) JPS53106672U (enExample)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4873077A (enExample) * 1971-12-29 1973-10-02
JPS4966073A (enExample) * 1972-10-27 1974-06-26

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4873077A (enExample) * 1971-12-29 1973-10-02
JPS4966073A (enExample) * 1972-10-27 1974-06-26

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