JPS53102642A - Decimal compensating circuit for subtraction - Google Patents

Decimal compensating circuit for subtraction

Info

Publication number
JPS53102642A
JPS53102642A JP1711577A JP1711577A JPS53102642A JP S53102642 A JPS53102642 A JP S53102642A JP 1711577 A JP1711577 A JP 1711577A JP 1711577 A JP1711577 A JP 1711577A JP S53102642 A JPS53102642 A JP S53102642A
Authority
JP
Japan
Prior art keywords
decimal
subtraction
compensating circuit
compensating
hardware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1711577A
Other languages
Japanese (ja)
Inventor
Kiyoshi Matsubara
Toshimasa Kihara
Tsuneo Funabashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1711577A priority Critical patent/JPS53102642A/en
Publication of JPS53102642A publication Critical patent/JPS53102642A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To realize the decimal compensating instruction for subtraction with addition of minimal scale of hardware.
JP1711577A 1977-02-21 1977-02-21 Decimal compensating circuit for subtraction Pending JPS53102642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1711577A JPS53102642A (en) 1977-02-21 1977-02-21 Decimal compensating circuit for subtraction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1711577A JPS53102642A (en) 1977-02-21 1977-02-21 Decimal compensating circuit for subtraction

Publications (1)

Publication Number Publication Date
JPS53102642A true JPS53102642A (en) 1978-09-07

Family

ID=11935024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1711577A Pending JPS53102642A (en) 1977-02-21 1977-02-21 Decimal compensating circuit for subtraction

Country Status (1)

Country Link
JP (1) JPS53102642A (en)

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