JPS5288569U - - Google Patents

Info

Publication number
JPS5288569U
JPS5288569U JP1975176812U JP17681275U JPS5288569U JP S5288569 U JPS5288569 U JP S5288569U JP 1975176812 U JP1975176812 U JP 1975176812U JP 17681275 U JP17681275 U JP 17681275U JP S5288569 U JPS5288569 U JP S5288569U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1975176812U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1975176812U priority Critical patent/JPS5288569U/ja
Publication of JPS5288569U publication Critical patent/JPS5288569U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
JP1975176812U 1975-12-25 1975-12-25 Pending JPS5288569U (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1975176812U JPS5288569U (enrdf_load_stackoverflow) 1975-12-25 1975-12-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1975176812U JPS5288569U (enrdf_load_stackoverflow) 1975-12-25 1975-12-25

Publications (1)

Publication Number Publication Date
JPS5288569U true JPS5288569U (enrdf_load_stackoverflow) 1977-07-01

Family

ID=28655116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1975176812U Pending JPS5288569U (enrdf_load_stackoverflow) 1975-12-25 1975-12-25

Country Status (1)

Country Link
JP (1) JPS5288569U (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011159768A (ja) * 2010-01-29 2011-08-18 Toshiba Corp Ledパッケージ及びledパッケージの製造方法
JP2011176264A (ja) * 2010-01-29 2011-09-08 Toshiba Corp Ledパッケージ

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4887776A (enrdf_load_stackoverflow) * 1972-02-18 1973-11-17
JPS5026768B1 (enrdf_load_stackoverflow) * 1969-09-11 1975-09-03

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5026768B1 (enrdf_load_stackoverflow) * 1969-09-11 1975-09-03
JPS4887776A (enrdf_load_stackoverflow) * 1972-02-18 1973-11-17

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011159768A (ja) * 2010-01-29 2011-08-18 Toshiba Corp Ledパッケージ及びledパッケージの製造方法
JP2011176264A (ja) * 2010-01-29 2011-09-08 Toshiba Corp Ledパッケージ

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