JPS5259557A - Phase loked loop - Google Patents

Phase loked loop

Info

Publication number
JPS5259557A
JPS5259557A JP50134648A JP13464875A JPS5259557A JP S5259557 A JPS5259557 A JP S5259557A JP 50134648 A JP50134648 A JP 50134648A JP 13464875 A JP13464875 A JP 13464875A JP S5259557 A JPS5259557 A JP S5259557A
Authority
JP
Japan
Prior art keywords
loked
loop
phase
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50134648A
Other languages
Japanese (ja)
Other versions
JPS5621310B2 (en
Inventor
Nobuaki Takahashi
Masao Kasuga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP50134648A priority Critical patent/JPS5259557A/en
Publication of JPS5259557A publication Critical patent/JPS5259557A/en
Publication of JPS5621310B2 publication Critical patent/JPS5621310B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
    • H03D3/24—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
    • H03D3/241—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits the oscillator being part of a phase locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:A filter and a differential circuit are provided in the circuit which demodulates angle-modulated wave signal, and normal operation is ensured even if the phase difference of the output signal and input signal of the voltage control oscillator exceeds90 deg., so that the lock range can be expanded by means of a simple construction.
JP50134648A 1975-11-11 1975-11-11 Phase loked loop Granted JPS5259557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50134648A JPS5259557A (en) 1975-11-11 1975-11-11 Phase loked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50134648A JPS5259557A (en) 1975-11-11 1975-11-11 Phase loked loop

Publications (2)

Publication Number Publication Date
JPS5259557A true JPS5259557A (en) 1977-05-17
JPS5621310B2 JPS5621310B2 (en) 1981-05-19

Family

ID=15133273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50134648A Granted JPS5259557A (en) 1975-11-11 1975-11-11 Phase loked loop

Country Status (1)

Country Link
JP (1) JPS5259557A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60169225A (en) * 1984-02-13 1985-09-02 Fujitsu Ltd Phase locked loop
JP2019153962A (en) * 2018-03-05 2019-09-12 ザインエレクトロニクス株式会社 PLL circuit and CDR device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60169225A (en) * 1984-02-13 1985-09-02 Fujitsu Ltd Phase locked loop
JP2019153962A (en) * 2018-03-05 2019-09-12 ザインエレクトロニクス株式会社 PLL circuit and CDR device
CN110233621A (en) * 2018-03-05 2019-09-13 哉英电子股份有限公司 PLL circuit and CDR device

Also Published As

Publication number Publication date
JPS5621310B2 (en) 1981-05-19

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