JPS5255410A - Serial-parallel conversion system - Google Patents

Serial-parallel conversion system

Info

Publication number
JPS5255410A
JPS5255410A JP50131646A JP13164675A JPS5255410A JP S5255410 A JPS5255410 A JP S5255410A JP 50131646 A JP50131646 A JP 50131646A JP 13164675 A JP13164675 A JP 13164675A JP S5255410 A JPS5255410 A JP S5255410A
Authority
JP
Japan
Prior art keywords
serial
parallel conversion
conversion system
data
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50131646A
Other languages
Japanese (ja)
Other versions
JPS5858875B2 (en
Inventor
Shunichi Naito
Takuto Kojima
Hiroaki Sato
Yoshio Kuboyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP50131646A priority Critical patent/JPS5858875B2/en
Publication of JPS5255410A publication Critical patent/JPS5255410A/en
Publication of JPS5858875B2 publication Critical patent/JPS5858875B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:The erading and writing is carried out by 1 bit for serial data, and the memory capable of reading and writing of parallel data is also equipped. Through the alternate switching of the above actions, the serial-parallel conversion is performed for the data. In this way, the serial-parallel conversion can be performed with minimized register number.
JP50131646A 1975-10-31 1975-10-31 Chiyokuretsuheiletsuhenkanhoushiki Expired JPS5858875B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50131646A JPS5858875B2 (en) 1975-10-31 1975-10-31 Chiyokuretsuheiletsuhenkanhoushiki

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50131646A JPS5858875B2 (en) 1975-10-31 1975-10-31 Chiyokuretsuheiletsuhenkanhoushiki

Publications (2)

Publication Number Publication Date
JPS5255410A true JPS5255410A (en) 1977-05-06
JPS5858875B2 JPS5858875B2 (en) 1983-12-27

Family

ID=15062911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50131646A Expired JPS5858875B2 (en) 1975-10-31 1975-10-31 Chiyokuretsuheiletsuhenkanhoushiki

Country Status (1)

Country Link
JP (1) JPS5858875B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6447152A (en) * 1987-08-18 1989-02-21 Nec Corp Digital cross connect network

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6447152A (en) * 1987-08-18 1989-02-21 Nec Corp Digital cross connect network

Also Published As

Publication number Publication date
JPS5858875B2 (en) 1983-12-27

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