JPS5255407A - Up-down separation type memory switch system - Google Patents

Up-down separation type memory switch system

Info

Publication number
JPS5255407A
JPS5255407A JP13164375A JP13164375A JPS5255407A JP S5255407 A JPS5255407 A JP S5255407A JP 13164375 A JP13164375 A JP 13164375A JP 13164375 A JP13164375 A JP 13164375A JP S5255407 A JPS5255407 A JP S5255407A
Authority
JP
Japan
Prior art keywords
type memory
switch system
separation type
memory switch
down separation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13164375A
Other languages
Japanese (ja)
Other versions
JPS5850476B2 (en
Inventor
Shunichi Naito
Takuto Kojima
Hiroaki Sato
Shuji Tomita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP13164375A priority Critical patent/JPS5850476B2/en
Publication of JPS5255407A publication Critical patent/JPS5255407A/en
Publication of JPS5850476B2 publication Critical patent/JPS5850476B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:In the time division conversion system, data pass memory is provided up and down in order to soften the memroy cycle of 1 time slot.
JP13164375A 1975-10-31 1975-10-31 Memory switch memory switch Expired JPS5850476B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13164375A JPS5850476B2 (en) 1975-10-31 1975-10-31 Memory switch memory switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13164375A JPS5850476B2 (en) 1975-10-31 1975-10-31 Memory switch memory switch

Publications (2)

Publication Number Publication Date
JPS5255407A true JPS5255407A (en) 1977-05-06
JPS5850476B2 JPS5850476B2 (en) 1983-11-10

Family

ID=15062841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13164375A Expired JPS5850476B2 (en) 1975-10-31 1975-10-31 Memory switch memory switch

Country Status (1)

Country Link
JP (1) JPS5850476B2 (en)

Also Published As

Publication number Publication date
JPS5850476B2 (en) 1983-11-10

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