JPS5252557A - Inverter circuit - Google Patents

Inverter circuit

Info

Publication number
JPS5252557A
JPS5252557A JP50129112A JP12911275A JPS5252557A JP S5252557 A JPS5252557 A JP S5252557A JP 50129112 A JP50129112 A JP 50129112A JP 12911275 A JP12911275 A JP 12911275A JP S5252557 A JPS5252557 A JP S5252557A
Authority
JP
Japan
Prior art keywords
inverter circuit
enhancement
channels
gate
units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50129112A
Other languages
Japanese (ja)
Inventor
Yoshihiro Ogata
Takeshi Yamada
Hironobu Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KIYOUDOU DENSHI GIJIYUTSU KENKIYUUJIYO KK
KYODO DENSHI GIJIYUTSU KENKIYU
KYODO DENSHI GIJUTSU KENKYUSHO KK
TOUKOU KK
Toko Inc
Original Assignee
KIYOUDOU DENSHI GIJIYUTSU KENKIYUUJIYO KK
KYODO DENSHI GIJIYUTSU KENKIYU
KYODO DENSHI GIJUTSU KENKYUSHO KK
TOUKOU KK
Toko Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KIYOUDOU DENSHI GIJIYUTSU KENKIYUUJIYO KK, KYODO DENSHI GIJIYUTSU KENKIYU, KYODO DENSHI GIJUTSU KENKYUSHO KK, TOUKOU KK, Toko Inc filed Critical KIYOUDOU DENSHI GIJIYUTSU KENKIYUUJIYO KK
Priority to JP50129112A priority Critical patent/JPS5252557A/en
Priority to DE19762616936 priority patent/DE2616936A1/en
Publication of JPS5252557A publication Critical patent/JPS5252557A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE: As for enhancement-type MOS inverter of P and N channels, each gate is driven by two units of input signal voltage of different phase in order to secure high speed and low power consumption.
COPYRIGHT: (C)1977,JPO&Japio
JP50129112A 1975-10-27 1975-10-27 Inverter circuit Pending JPS5252557A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP50129112A JPS5252557A (en) 1975-10-27 1975-10-27 Inverter circuit
DE19762616936 DE2616936A1 (en) 1975-10-27 1976-04-17 Static inverter with two complementary MOSFETs - with feedback to one gate causing oscillation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50129112A JPS5252557A (en) 1975-10-27 1975-10-27 Inverter circuit

Publications (1)

Publication Number Publication Date
JPS5252557A true JPS5252557A (en) 1977-04-27

Family

ID=15001354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50129112A Pending JPS5252557A (en) 1975-10-27 1975-10-27 Inverter circuit

Country Status (2)

Country Link
JP (1) JPS5252557A (en)
DE (1) DE2616936A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59140725A (en) * 1983-01-31 1984-08-13 Nec Corp Logical circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4410211B4 (en) * 1994-03-24 2005-07-21 Atmel Germany Gmbh Circuit arrangement for the switchable control of a load

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5057161A (en) * 1973-09-17 1975-05-19
JPS5086967A (en) * 1973-11-30 1975-07-12

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5057161A (en) * 1973-09-17 1975-05-19
JPS5086967A (en) * 1973-11-30 1975-07-12

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59140725A (en) * 1983-01-31 1984-08-13 Nec Corp Logical circuit

Also Published As

Publication number Publication date
DE2616936A1 (en) 1977-05-05

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