JPS525248A - Latch circuit - Google Patents

Latch circuit

Info

Publication number
JPS525248A
JPS525248A JP51060686A JP6068676A JPS525248A JP S525248 A JPS525248 A JP S525248A JP 51060686 A JP51060686 A JP 51060686A JP 6068676 A JP6068676 A JP 6068676A JP S525248 A JPS525248 A JP S525248A
Authority
JP
Japan
Prior art keywords
latch circuit
latch
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP51060686A
Other languages
English (en)
Japanese (ja)
Inventor
Pii Supanpinato Dominitsuku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS525248A publication Critical patent/JPS525248A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356017Bistable circuits using additional transistors in the input circuit
    • H03K3/356052Bistable circuits using additional transistors in the input circuit using pass gates
    • H03K3/35606Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16504Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
    • G01R19/16519Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356069Bistable circuits using additional transistors in the feedback circuit
    • H03K3/356078Bistable circuits using additional transistors in the feedback circuit with synchronous operation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356086Bistable circuits with additional means for controlling the main nodes
    • H03K3/356095Bistable circuits with additional means for controlling the main nodes with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Shift Register Type Memory (AREA)
JP51060686A 1975-06-30 1976-05-27 Latch circuit Pending JPS525248A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US59198375A 1975-06-30 1975-06-30

Publications (1)

Publication Number Publication Date
JPS525248A true JPS525248A (en) 1977-01-14

Family

ID=24368774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51060686A Pending JPS525248A (en) 1975-06-30 1976-05-27 Latch circuit

Country Status (4)

Country Link
JP (1) JPS525248A (tr)
DE (1) DE2624228A1 (tr)
FR (1) FR2316791A1 (tr)
IT (1) IT1064304B (tr)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1904787B2 (de) * 1969-01-31 1977-07-21 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Elektrisches speicherelement und betrieb desselben

Also Published As

Publication number Publication date
IT1064304B (it) 1985-02-18
FR2316791B1 (tr) 1978-11-17
DE2624228A1 (de) 1977-02-03
FR2316791A1 (fr) 1977-01-28

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