JPS524724A - Synchronizing circuit - Google Patents

Synchronizing circuit

Info

Publication number
JPS524724A
JPS524724A JP50080676A JP8067675A JPS524724A JP S524724 A JPS524724 A JP S524724A JP 50080676 A JP50080676 A JP 50080676A JP 8067675 A JP8067675 A JP 8067675A JP S524724 A JPS524724 A JP S524724A
Authority
JP
Japan
Prior art keywords
synchronizing circuit
bit rate
amount per
rate increases
per channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50080676A
Other languages
Japanese (ja)
Other versions
JPS5726456B2 (en
Inventor
Kozo Murakami
Akira Hattori
Yuzo Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP50080676A priority Critical patent/JPS524724A/en
Publication of JPS524724A publication Critical patent/JPS524724A/en
Publication of JPS5726456B2 publication Critical patent/JPS5726456B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To obtain synchronizing circuit, which can minimize hardware amount per channel as transmission bit rate increases.
JP50080676A 1975-06-30 1975-06-30 Synchronizing circuit Granted JPS524724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50080676A JPS524724A (en) 1975-06-30 1975-06-30 Synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50080676A JPS524724A (en) 1975-06-30 1975-06-30 Synchronizing circuit

Publications (2)

Publication Number Publication Date
JPS524724A true JPS524724A (en) 1977-01-14
JPS5726456B2 JPS5726456B2 (en) 1982-06-04

Family

ID=13724945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50080676A Granted JPS524724A (en) 1975-06-30 1975-06-30 Synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS524724A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6386630A (en) * 1986-09-29 1988-04-18 Nec Corp Frame synchronization system in parallel transmission line
US6441664B2 (en) 1999-12-10 2002-08-27 Fujitsu Limited Signal phase adjustment circuit to set optimum phase

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6386630A (en) * 1986-09-29 1988-04-18 Nec Corp Frame synchronization system in parallel transmission line
US6441664B2 (en) 1999-12-10 2002-08-27 Fujitsu Limited Signal phase adjustment circuit to set optimum phase
US6570424B2 (en) 1999-12-10 2003-05-27 Fujitsu Limited Signal phase adjustment circuit to set optimum phase
US6586983B2 (en) 1999-12-10 2003-07-01 Fujitsu Limited Signal phase adjustment circuit to set optimum phase

Also Published As

Publication number Publication date
JPS5726456B2 (en) 1982-06-04

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